spi25: Implement multi-i/o reads
We describe a read operation in a new `struct spi_read_op`. It's
comprised of the i/o mode, its opcode, an optional mode byte, and
the number of dummy bytes.
Based on this information about the various read operations, and
the flash and master feature flags, we select the read operation
with the highest throughput.
The following assumption is made about 4BA chips: When it supports
native-4BA fast reads and a multi-i/o version of the regular fast
read, then it should also support the respective native-4BA, multi-
i/o version (yes, JEDEC, there are too many read commands!). So far
this seems to hold for the chips in our database.
Change-Id: I3c93e71d85f769831d637c14d3571f7ddb54d8b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/49
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
diff --git a/include/spi.h b/include/spi.h
index 8935997..9cf5154 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -194,9 +194,11 @@
#define JEDEC_READ 0x03
#define JEDEC_READ_OUTSIZE 0x04
/* JEDEC_READ_INSIZE : any length */
-
-/* Read the memory (with delay after sending address) */
-#define JEDEC_READ_FAST 0x0b
+#define JEDEC_FAST_READ 0x0b /* with 8 cycles delay after sending address */
+#define JEDEC_FAST_READ_DOUT 0x3b /* with 8 cycles delay and dual output */
+#define JEDEC_FAST_READ_DIO 0xbb /* with 4 cycles delay and dual i/o */
+#define JEDEC_FAST_READ_QOUT 0x6b /* with 8 cycles delay and quad output */
+#define JEDEC_FAST_READ_QIO 0xeb /* with 6 cycles delay and quad i/o */
/* Write memory byte */
#define JEDEC_BYTE_PROGRAM 0x02
@@ -211,11 +213,12 @@
/* Read the memory with 4-byte address
From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
-#define JEDEC_READ_4BA 0x13
-
-/* Read the memory with 4-byte address (and delay after sending address)
- From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */
-#define JEDEC_READ_4BA_FAST 0x0c
+#define JEDEC_READ_4BA 0x13
+#define JEDEC_FAST_READ_4BA 0x0c /* with 8 cycles delay after sending address */
+#define JEDEC_FAST_READ_DOUT_4BA 0x3c /* with 8 cycles delay and dual output */
+#define JEDEC_FAST_READ_DIO_4BA 0xbc /* with 4 cycles delay and dual i/o */
+#define JEDEC_FAST_READ_QOUT_4BA 0x6c /* with 8 cycles delay and quad output */
+#define JEDEC_FAST_READ_QIO_4BA 0xec /* with 6 cycles delay and quad i/o */
/* Write memory byte with 4-byte address
From ANY mode (3-bytes or 4-bytes) it works with 4-byte address */