spi25_statusreg: Allow WRSR_EXT for Status Register 3
Spansion flash chips S25FL128L and S25FL256L use the WRSR instruction to
write more than 2 registers. So align SR2 and SR3 support: The current
FEATURE_WRSR_EXT is renamed to FEATURE_WRSR_EXT2 and FEATURE_WRSR_EXT3
is added. Also, WRSR3 needs a separate flag now.
Verified that FEATURE_WRSR_EXT2 still works using the `dummy_flasher`.
Signed-off-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ibdfc6eb3d2cfecbf8da0493d067031ddb079a094
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/64746
Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/flash.h b/flash.h
index 80c129c..c77522d 100644
--- a/flash.h
+++ b/flash.h
@@ -144,8 +144,10 @@
#define FEATURE_ERASED_ZERO (1 << 17)
#define FEATURE_NO_ERASE (1 << 18)
-#define FEATURE_WRSR_EXT (1 << 19)
+#define FEATURE_WRSR_EXT2 (1 << 19)
#define FEATURE_WRSR2 (1 << 20)
+#define FEATURE_WRSR_EXT3 ((1 << 21) | FEATURE_WRSR_EXT2)
+#define FEATURE_WRSR3 (1 << 22)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)