tree 74d3bec50d87ac2fc45c1c2beaf5d780e6acda4a
parent a358b14d2e7e93e317499a687223ada2d221a36a
author Sergii Dmytruk <sergii.dmytruk@3mdeb.com> 1638018867 +0200
committer Nico Huber <nico.h@gmx.de> 1721642927 +0000

spi25_statusreg.c: support reading security register

Not to be confused with "secure registers" of OTP.

Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing special write commands
with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL
commands). No WREN is necessary, but at least some datasheets indicate
BUSY state after those write commands.

Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.

The register is found in at least these chips by Macronix:
 * MX25L6436E
 * MX25L6445E
 * MX25L6465E
 * MX25L6473E

Ported to flashprog w/o the FEATURE_SCUR flag, we'll already have that
information in the register description.

Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/71006
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>