diff --git a/include/flash.h b/include/flash.h
index cfc9c4e..f2a1818 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -185,6 +185,7 @@
 	STATUS1,
 	STATUS2,
 	STATUS3,
+	SECURITY,
 	MAX_REGISTERS
 };
 
diff --git a/include/spi.h b/include/spi.h
index dc09b8e..9e655fc 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -161,6 +161,16 @@
 #define JEDEC_WRSR3_OUTSIZE	0x02
 #define JEDEC_WRSR3_INSIZE	0x00
 
+/* Read Security Register */
+#define JEDEC_RDSCUR		0x2b
+#define JEDEC_RDSCUR_OUTSIZE	0x01
+#define JEDEC_RDSCUR_INSIZE	0x01
+
+/* Write Security Register */
+#define JEDEC_WRSCUR		0x2f
+#define JEDEC_WRSCUR_OUTSIZE	0x01
+#define JEDEC_WRSCUR_INSIZE	0x00
+
 /* Enter 4-byte Address Mode */
 #define JEDEC_ENTER_4_BYTE_ADDR_MODE	0xB7
 
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 5dbba75..1e6a870 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -100,6 +100,13 @@
 		}
 		msg_cerr("Cannot write SR3: unsupported by chip\n");
 		return 1;
+	case SECURITY:
+		/*
+		 * Security register doesn't have a normal write operation. Instead,
+		 * there are separate commands that set individual OTP bits.
+		 */
+		msg_cerr("Cannot write SECURITY: unsupported by design\n");
+		return 1;
 	default:
 		msg_cerr("Cannot write register: unknown register\n");
 		return 1;
@@ -195,6 +202,9 @@
 		}
 		msg_cerr("Cannot read SR3: unsupported by chip\n");
 		return 1;
+	case SECURITY:
+		read_cmd = JEDEC_RDSCUR;
+		break;
 	default:
 		msg_cerr("Cannot read register: unknown register\n");
 		return 1;