spi25_statusreg.c: support reading security register
Not to be confused with "secure registers" of OTP.
Security register is a dedicated status register for security-related
bits. You don't write its value directly, issuing special write commands
with no data set separate OTP bits to 1 automatically (WRSCUR, WPSEL
commands). No WREN is necessary, but at least some datasheets indicate
BUSY state after those write commands.
Unlike cases where OTP bit is part of SR and can only be written while
in OTP mode, security register can only be written outside of the mode.
The register is found in at least these chips by Macronix:
* MX25L6436E
* MX25L6445E
* MX25L6465E
* MX25L6473E
Ported to flashprog w/o the FEATURE_SCUR flag, we'll already have that
information in the register description.
Change-Id: Iae1753ca4cb051127a5bcbeba7f064053adb8dae
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/59709
Original-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/71006
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: Nico Huber <nico.h@gmx.de>
diff --git a/include/flash.h b/include/flash.h
index cfc9c4e..f2a1818 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -185,6 +185,7 @@
STATUS1,
STATUS2,
STATUS3,
+ SECURITY,
MAX_REGISTERS
};
diff --git a/include/spi.h b/include/spi.h
index dc09b8e..9e655fc 100644
--- a/include/spi.h
+++ b/include/spi.h
@@ -161,6 +161,16 @@
#define JEDEC_WRSR3_OUTSIZE 0x02
#define JEDEC_WRSR3_INSIZE 0x00
+/* Read Security Register */
+#define JEDEC_RDSCUR 0x2b
+#define JEDEC_RDSCUR_OUTSIZE 0x01
+#define JEDEC_RDSCUR_INSIZE 0x01
+
+/* Write Security Register */
+#define JEDEC_WRSCUR 0x2f
+#define JEDEC_WRSCUR_OUTSIZE 0x01
+#define JEDEC_WRSCUR_INSIZE 0x00
+
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7