tree 6a40ff5ca048148294b209d8cb99ab9558fdc44f
parent b57f48f77f367c43cd83878d92aa55de151c0798
author Angel Pons <th3fanbus@gmail.com> 1586948382 +0200
committer Felix Singer <felixsinger@posteo.net> 1664471093 +0000

chipset_enable.c: Disable SPI on ICH7 if booted from LPC

Commit 92d6a86 ("Refactor Intel Chipset Enables") eliminated a check
to disable SPI when ICH7 has booted from LPC, as the hardware does not
support it. Therefore, when flashrom probes the SPI bus, it times out
waiting for the hardware to react, for each and every SPI flash chip.
This results in very long delays and countless instances of the error:

    Error: SCIP never cleared!

To prevent this, bring back part of the lost check. Probing for LPC and
FWH when booted from SPI does not seem to cause any problems on desktop
mainboards with ICH7, so don't disable LPC nor FWH if that is the case.

Tested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.

Change-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/40401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67863
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Singer <felixsinger@posteo.net>