)]}'
{
  "commit": "399a4dd721a64a1d22e2f8028cc39d6496515ed6",
  "tree": "6a40ff5ca048148294b209d8cb99ab9558fdc44f",
  "parents": [
    "b57f48f77f367c43cd83878d92aa55de151c0798"
  ],
  "author": {
    "name": "Angel Pons",
    "email": "th3fanbus@gmail.com",
    "time": "Wed Apr 15 12:59:42 2020 +0200"
  },
  "committer": {
    "name": "Felix Singer",
    "email": "felixsinger@posteo.net",
    "time": "Thu Sep 29 17:04:53 2022 +0000"
  },
  "message": "chipset_enable.c: Disable SPI on ICH7 if booted from LPC\n\nCommit 92d6a86 (\"Refactor Intel Chipset Enables\") eliminated a check\nto disable SPI when ICH7 has booted from LPC, as the hardware does not\nsupport it. Therefore, when flashrom probes the SPI bus, it times out\nwaiting for the hardware to react, for each and every SPI flash chip.\nThis results in very long delays and countless instances of the error:\n\n    Error: SCIP never cleared!\n\nTo prevent this, bring back part of the lost check. Probing for LPC and\nFWH when booted from SPI does not seem to cause any problems on desktop\nmainboards with ICH7, so don\u0027t disable LPC nor FWH if that is the case.\n\nTested on ECS 945G-M4 (ICH7, boots from LPC), works without errors.\n\nChange-Id: I5e59e66a2dd16b07f2dca410997fce38ab9c8fd1\nSigned-off-by: Angel Pons \u003cth3fanbus@gmail.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/40401\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: HAOUAS Elyes \u003cehaouas@noos.fr\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom/+/67863\nReviewed-by: Elyes Haouas \u003cehaouas@noos.fr\u003e\nReviewed-by: Felix Singer \u003cfelixsinger@posteo.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "84e4b6b5c6f210add57e654cb64eb51ed810dec4",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "0dfe26756ddda375c1d13ede9faac0d9d5c0b4a9",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    }
  ]
}