)]}'
{
  "commit": "39446e34c8d14f6a9798dae17ee0152263a31744",
  "tree": "91cb5ba77510f0118668b48c617fcbb2a4278914",
  "parents": [
    "9ad4255b5e206899351b446dec96b84c989627b6"
  ],
  "author": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 12:02:07 2010 +0000"
  },
  "committer": {
    "name": "Carl-Daniel Hailfinger",
    "email": "c-d.hailfinger.devel.2006@gmx.net",
    "time": "Wed Sep 15 12:02:07 2010 +0000"
  },
  "message": "Detect embedded EC (IMC) in AMD\u0027s SBs\n\nAMD SB700 and later have an integrated microcontroller (IMC) which runs\nfrom shared flash.\n\nThe IMC will happily issue reads while we write, issue writes while we\nread, and generally cause lots of havoc due to the concurrent accesses\nit performs while flashrom is running. A failing or corrupted read can\nbe detected since r1145, and the worst case is that the read aborts and\nthe user has to retry. A failing write is much more serious. It can\nbe detected since r1145, but if the SPI interface locks up, we can\u0027t\ncontinue writing nor can we read the current chip contents.\n\nIf the IMC is inactive, there is no reason to worry. If the IMC is\nactive, flashrom will refuse to erase/write the chip with this patch.\n\nThe correct fix would be to stop the IMC during flashing, but apparently\nthe relevant registers are undocumented, so we take the safe route for\nnow until someone from AMD can give us more info.\n\nCorresponding to flashrom svn r1173.\n\nSigned-off-by: Carl-Daniel Hailfinger \u003cc-d.hailfinger.devel.2006@gmx.net\u003e\nTested-by: Matthias Kretz \u003ckretz@kde.org\u003e\nAcked-by: Uwe Hermann \u003cuwe@hermann-uwe.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "c20d5e6b884240423d3a16ffb134f0b9d0966376",
      "old_mode": 33188,
      "old_path": "sb600spi.c",
      "new_id": "4e3e07956d293b0b391a8c769bc04d78dea80c7e",
      "new_mode": 33188,
      "new_path": "sb600spi.c"
    }
  ]
}