Coding-style fixes for flashrom, partly indent-aided
Corresponding to flashrom svn r326 and coreboot v2 svn r3669.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
diff --git a/board_enable.c b/board_enable.c
index e2a87c6..0834828 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -357,7 +357,7 @@
uint16_t port;
uint8_t val;
- dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */
+ dev = pci_dev_find(0x8086, 0x2440); /* Intel ICH2 LPC */
if (!dev) {
fprintf(stderr, "\nERROR: ICH2 LPC bridge not found.\n");
return -1;
@@ -367,8 +367,8 @@
port = (pci_read_word(dev, 0x58) & 0xFFC0) + 0xE;
val = INB(port);
- val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
- val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
+ val |= 0x80; /* Top Block Lock -- pin 8 of PLCC32 */
+ val |= 0x40; /* Lower Blocks Lock -- pin 7 of PLCC32 */
OUTB(val, port);
return 0;
@@ -405,7 +405,7 @@
return -1;
}
- if (read(msr_fd, (void*) msr, 8) != 8) {
+ if (read(msr_fd, (void *)msr, 8) != 8) {
perror("read");
close(msr_fd);
return -1;
@@ -419,7 +419,7 @@
msr[0] &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
msr[0] |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
- (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
+ (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
perror("lseek");
@@ -427,7 +427,7 @@
return -1;
}
- if (write(msr_fd, (void*) msr, 8) != 8) {
+ if (write(msr_fd, (void *)msr, 8) != 8) {
perror("write");
close(msr_fd);
return -1;
@@ -458,7 +458,7 @@
uint16_t gpiobar;
uint32_t reg32;
- dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */
+ dev = pci_dev_find(ich_vendor, ich_device); /* Intel ICHx LPC */
if (!dev) {
fprintf(stderr, "\nERROR: ICHx LPC dev %4x:%4x not found.\n",
ich_vendor, ich_device);
@@ -492,7 +492,7 @@
#define ICH7_GPIO_LVL2 0x38
- dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */
+ dev = pci_dev_find(0x8086, 0x27b8); /* Intel ICH7 LPC */
if (!dev) {
// This will never happen on this board
fprintf(stderr, "\nERROR: ICH7 LPC bridge not found.\n");
@@ -664,12 +664,12 @@
"artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x},
{0x1022, 0x2090, 0x0000, 0x0000, 0x1022, 0x2080, 0x0000, 0x0000,
"artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x},
- {0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m},
- {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202,
- NULL, NULL, "BioStar P4M80-M4", board_biostar_p4m80_m4},
- {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000,
- NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4},
+ {0x8086, 0x27b8, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
+ "kontron", "986lcd-m", "Kontron 986LCD-M", board_kontron_986lcd_m},
+ {0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202,
+ NULL, NULL, "BioStar P4M80-M4", board_biostar_p4m80_m4},
+ {0x1106, 0x3227, 0x1458, 0x5001, 0x10ec, 0x8139, 0x1458, 0xe000,
+ NULL, NULL, "GIGABYTE GA-7VT600", board_biostar_p4m80_m4},
{0x1106, 0x3149, 0x1462, 0x7094, 0x10ec, 0x8167, 0x1462, 0x094c,
NULL, NULL, "MSI K8T Neo2", w83627thf_gpio4_4_raise_2e},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
@@ -699,13 +699,15 @@
* Match boards on coreboot table gathered vendor and part name.
* Require main PCI IDs to match too as extra safety.
*/
-static struct board_pciid_enable *board_match_coreboot_name(const char *vendor, const char *part)
+static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
+ const char *part)
{
struct board_pciid_enable *board = board_pciid_enables;
struct board_pciid_enable *partmatch = NULL;
for (; board->name; board++) {
- if (vendor && (!board->lb_vendor || strcasecmp(board->lb_vendor, vendor)))
+ if (vendor && (!board->lb_vendor
+ || strcasecmp(board->lb_vendor, vendor)))
continue;
if (!board->lb_part || strcasecmp(board->lb_part, part))
@@ -715,7 +717,7 @@
continue;
if (board->second_vendor &&
- !pci_dev_find(board->second_vendor, board->second_device))
+ !pci_dev_find(board->second_vendor, board->second_device))
continue;
if (vendor)
@@ -725,7 +727,7 @@
/* a second entry has a matching part name */
printf("AMBIGUOUS BOARD NAME: %s\n", part);
printf("At least vendors '%s' and '%s' match.\n",
- partmatch->lb_vendor, board->lb_vendor);
+ partmatch->lb_vendor, board->lb_vendor);
printf("Please use the full -m vendor:part syntax.\n");
return NULL;
}
@@ -752,20 +754,20 @@
continue;
if (!pci_card_find(board->first_vendor, board->first_device,
- board->first_card_vendor,
- board->first_card_device))
+ board->first_card_vendor,
+ board->first_card_device))
continue;
if (board->second_vendor) {
if (board->second_card_vendor) {
if (!pci_card_find(board->second_vendor,
- board->second_device,
- board->second_card_vendor,
- board->second_card_device))
+ board->second_device,
+ board->second_card_vendor,
+ board->second_card_device))
continue;
} else {
if (!pci_dev_find(board->second_vendor,
- board->second_device))
+ board->second_device))
continue;
}
}
@@ -789,7 +791,7 @@
if (board) {
printf("Found board \"%s\", enabling flash write... ",
- board->name);
+ board->name);
ret = board->enable(board->name);
if (ret)
diff --git a/chipset_enable.c b/chipset_enable.c
index 3ad99cc..86c731b 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -45,7 +45,6 @@
flashbus_t flashbus = BUS_TYPE_LPC;
void *spibar = NULL;
-
static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
{
uint8_t tmp;
@@ -201,27 +200,30 @@
#define ICH_STRAP_PCI 0x02
#define ICH_STRAP_LPC 0x03
-static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
+static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
+{
uint32_t mmio_base;
mmio_base = (pci_read_long(dev, 0xbc)) << 8;
printf_debug("MMIO base at = 0x%x\n", mmio_base);
- spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
- fd_mem, mmio_base);
+ spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
+ fd_mem, mmio_base);
if (spibar == MAP_FAILED) {
perror("Can't mmap memory using " MEM_DEV);
exit(1);
}
- printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(spibar + 0x6c));
+ printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
+ *(uint16_t *) (spibar + 0x6c));
flashbus = BUS_TYPE_VIA_SPI;
return 0;
}
-static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation)
+static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
+ int ich_generation)
{
int ret, i;
uint8_t old, new, bbs, buc;
@@ -229,7 +231,7 @@
uint32_t tmp, gcs;
void *rcrb;
static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
-
+
/* Enable Flash Writes */
ret = enable_flash_ich_dc(dev, name);
@@ -238,7 +240,8 @@
printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
/* Map RCBA to virtual memory */
- rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
+ rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem,
+ (off_t) tmp);
if (rcrb == MAP_FAILED) {
perror("Can't mmap memory using " MEM_DEV);
exit(1);
@@ -252,7 +255,8 @@
printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
buc = *(volatile uint8_t *)(rcrb + 0x3414);
- printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
+ printf_debug("Top Swap : %s\n",
+ (buc & 1) ? "enabled (A16 inverted)" : "not enabled");
/* It seems the ICH7 does not support SPI and LPC chips at the same
* time. At least not with our current code. So we prevent searching
@@ -275,7 +279,7 @@
break;
case 9:
case 10:
- default: /* Future version might behave the same */
+ default: /* Future version might behave the same */
flashbus = BUS_TYPE_ICH9_SPI;
spibar_offset = 0x3800;
break;
@@ -285,31 +289,42 @@
printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
/* Assign Virtual Address */
- spibar = rcrb + spibar_offset;
+ spibar = rcrb + spibar_offset;
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
- printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0));
- printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2));
- printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4));
- for (i=0; i < 8; i++) {
+ printf_debug("0x00: 0x%04x (SPIS)\n",
+ *(uint16_t *) (spibar + 0));
+ printf_debug("0x02: 0x%04x (SPIC)\n",
+ *(uint16_t *) (spibar + 2));
+ printf_debug("0x04: 0x%08x (SPIA)\n",
+ *(uint32_t *) (spibar + 4));
+ for (i = 0; i < 8; i++) {
int offs;
offs = 8 + (i * 8);
- printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i);
- printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i);
+ printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
+ *(uint32_t *) (spibar + offs), i);
+ printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
+ *(uint32_t *) (spibar + offs + 4), i);
}
- printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50));
- printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54));
- printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56));
- printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58));
- printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c));
- for (i=0; i < 4; i++) {
+ printf_debug("0x50: 0x%08x (BBAR)\n",
+ *(uint32_t *) (spibar + 0x50));
+ printf_debug("0x54: 0x%04x (PREOP)\n",
+ *(uint16_t *) (spibar + 0x54));
+ printf_debug("0x56: 0x%04x (OPTYPE)\n",
+ *(uint16_t *) (spibar + 0x56));
+ printf_debug("0x58: 0x%08x (OPMENU)\n",
+ *(uint32_t *) (spibar + 0x58));
+ printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
+ *(uint32_t *) (spibar + 0x5c));
+ for (i = 0; i < 4; i++) {
int offs;
offs = 0x60 + (i * 4);
- printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i);
+ printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
+ *(uint32_t *) (spibar + offs), i);
}
printf_debug("\n");
- if ( (*(uint16_t *)spibar) & (1 << 15)) {
+ if ((*(uint16_t *) spibar) & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
}
break;
@@ -332,8 +347,8 @@
case 1:
case 2:
printf_debug("prefetching %sabled, caching %sabled, ",
- (new & 0x2) ? "en" : "dis",
- (new & 0x1) ? "dis" : "en");
+ (new & 0x2) ? "en" : "dis",
+ (new & 0x1) ? "dis" : "en");
break;
default:
printf_debug("invalid prefetching/caching settings, ");
@@ -367,7 +382,7 @@
{
uint8_t val;
- /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF*/
+ /* enable ROM decode range (1MB) FFC00000 - FFFFFFFF */
pci_write_byte(dev, 0x41, 0x7f);
/* ROM write enable */
@@ -388,13 +403,13 @@
{
uint8_t reg8;
- #define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
- #define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
+#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
+#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
- #define LOWER_ROM_ADDRESS_RANGE (1 << 0)
- #define ROM_WRITE_ENABLE (1 << 1)
- #define UPPER_ROM_ADDRESS_RANGE (1 << 2)
- #define BIOS_ROM_POSITIVE_DECODE (1 << 5)
+#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
+#define ROM_WRITE_ENABLE (1 << 1)
+#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
+#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
/* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
@@ -433,8 +448,8 @@
*/
static int enable_flash_cs5536(struct pci_dev *dev, const char *name)
{
- #define MSR_RCONF_DEFAULT 0x1808
- #define MSR_NORF_CTL 0x51400018
+#define MSR_RCONF_DEFAULT 0x1808
+#define MSR_NORF_CTL 0x51400018
int fd_msr;
unsigned char buf[8];
@@ -460,7 +475,8 @@
if (buf[7] != 0x22) {
buf[7] &= 0xfb;
- if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT, SEEK_SET) == -1) {
+ if (lseek64(fd_msr, (off64_t) MSR_RCONF_DEFAULT,
+ SEEK_SET) == -1) {
perror("lseek64");
close(fd_msr);
return -1;
@@ -501,8 +517,8 @@
close(fd_msr);
- #undef MSR_RCONF_DEFAULT
- #undef MSR_NORF_CTL
+#undef MSR_RCONF_DEFAULT
+#undef MSR_NORF_CTL
return 0;
}
@@ -541,11 +557,11 @@
}
/* Extended BIOS enable = 1, Lower BIOS Enable = 1 */
- new = pci_read_byte(dev,0x40);
+ new = pci_read_byte(dev, 0x40);
new &= 0xFB;
new |= 0x3;
- pci_write_byte(dev,0x40,new);
- newer = pci_read_byte(dev,0x40);
+ pci_write_byte(dev, 0x40, new);
+ newer = pci_read_byte(dev, 0x40);
if (newer != new) {
printf("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
printf("Stuck at 0x%x\n", newer);
@@ -588,7 +604,7 @@
uint8_t reg;
/* Clear ROM Protect 0-3 */
- for (reg = 0x50; reg < 0x60; reg+=4) {
+ for (reg = 0x50; reg < 0x60; reg += 4) {
old = pci_read_long(dev, reg);
new = old & 0xFFFFFFFC;
if (new != old) {
@@ -642,9 +658,8 @@
f.device = 0x4372;
for (smbusdev = pacc->devices; smbusdev; smbusdev = smbusdev->next) {
- if (pci_filter_match(&f, smbusdev)) {
+ if (pci_filter_match(&f, smbusdev))
break;
- }
}
if (!smbusdev) {
@@ -697,9 +712,7 @@
pci_write_byte(dev, 0x6d, new);
if (pci_read_byte(dev, 0x6d) != new) {
- printf
- ("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n",
- 0x6d, new, name);
+ printf("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
return -1;
}
diff --git a/flash.h b/flash.h
index 35f7ab4..bce4844 100644
--- a/flash.h
+++ b/flash.h
@@ -54,7 +54,8 @@
struct flashchip {
const char *vendor;
const char *name;
- /* With 32bit manufacture_id and model_id we can cover IDs up to
+ /*
+ * With 32bit manufacture_id and model_id we can cover IDs up to
* (including) the 4th bank of JEDEC JEP106W Standard Manufacturer's
* Identification code.
*/
@@ -64,7 +65,8 @@
int total_size;
int page_size;
- /* Indicate if flashrom has been tested with this flash chip and if
+ /*
+ * Indicate if flashrom has been tested with this flash chip and if
* everything worked correctly.
*/
uint32_t tested;
@@ -149,7 +151,7 @@
#define CATALYST_ID 0x31 /* Catalyst */
-#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage*/
+#define EMST_ID 0x8C /* EMST / EFST Elite Flash Storage */
#define EMST_F49B002UA 0x00
/*
@@ -179,7 +181,8 @@
#define EN_29F002B 0x7F97
#define FUJITSU_ID 0x04 /* Fujitsu */
-/* MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
+/*
+ * MBM29F400TC_STRANGE has a value not mentioned in the data sheet and we
* try to read it from a location not mentioned in the data sheet.
*/
#define MBM29F400TC_STRANGE 0x23
@@ -215,8 +218,9 @@
#define MX_25L3235D 0x2416
#define MX_29F002 0xB0
-/* Programmable Micro Corp is listed in JEP106W in bank 2, so it should have
- * a 0x7F continuation code prefix.
+/*
+ * Programmable Micro Corp is listed in JEP106W in bank 2, so it should
+ * have a 0x7F continuation code prefix.
*/
#define PMC_ID 0x7F9D /* PMC */
#define PMC_ID_NOPREFIX 0x9D /* PMC, missing 0x7F prefix */
@@ -366,7 +370,6 @@
struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
uint16_t card_vendor, uint16_t card_device);
-
/* board_enable.c */
int board_flash_enable(const char *vendor, const char *part);
void print_supported_boards(void);
@@ -416,7 +419,8 @@
int probe_spi_rdid(struct flashchip *flash);
int probe_spi_rdid4(struct flashchip *flash);
int probe_spi_res(struct flashchip *flash);
-int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
+int spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
void spi_write_enable();
void spi_write_disable();
int spi_chip_erase_c7(struct flashchip *flash);
@@ -443,14 +447,16 @@
int write_en29f002a(struct flashchip *flash, uint8_t *buf);
/* ichspi.c */
-int ich_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
+int ich_spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
int ich_spi_read(struct flashchip *flash, uint8_t * buf);
int ich_spi_write(struct flashchip *flash, uint8_t * buf);
/* it87spi.c */
extern uint16_t it8716f_flashport;
int it87xx_probe_spi_flash(const char *name);
-int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr);
+int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr);
int it8716f_spi_chip_read(struct flashchip *flash, uint8_t *buf);
int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf);
diff --git a/flashrom.c b/flashrom.c
index 093f2ea..4f1b488 100644
--- a/flashrom.c
+++ b/flashrom.c
@@ -74,8 +74,10 @@
for (temp = pacc->devices; temp; temp = temp->next)
if (pci_filter_match(&filter, temp)) {
- if ((card_vendor == pci_read_word(temp, PCI_SUBSYSTEM_VENDOR_ID)) &&
- (card_device == pci_read_word(temp, PCI_SUBSYSTEM_ID)))
+ if ((card_vendor ==
+ pci_read_word(temp, PCI_SUBSYSTEM_VENDOR_ID))
+ && (card_device ==
+ pci_read_word(temp, PCI_SUBSYSTEM_ID)))
return temp;
}
@@ -131,7 +133,6 @@
*/
size = getpagesize();
}
-
#ifdef TS5300
// FIXME: Wrong place for this decision
// FIXME: This should be autodetected. It is trivial.
@@ -154,7 +155,8 @@
if (flash->probe(flash) != 1)
goto notfound;
- if (first_flash == flashchips || flash->model_id != GENERIC_DEVICE_ID)
+ if (first_flash == flashchips
+ || flash->model_id != GENERIC_DEVICE_ID)
break;
notfound:
@@ -193,7 +195,7 @@
printf("0x%08x ", idx);
}
printf("FAILED! Expected=0x%02x, Read=0x%02x\n",
- *(buf + idx), *(buf2 + idx));
+ *(buf + idx), *(buf2 + idx));
return 1;
}
@@ -220,7 +222,8 @@
void usage(const char *name)
{
- printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n", name);
+ printf("usage: %s [-rwvEVfLhR] [-c chipname] [-s exclude_start]\n",
+ name);
printf(" [-e exclude_end] [-m [vendor:]part] [-l file.layout] [-i imagename] [file]\n");
printf
(" -r | --read: read flash and save into file\n"
@@ -383,8 +386,7 @@
#else
if (iopl(3) != 0) {
#endif
- fprintf(stderr, "ERROR: Could not get IO privileges (%s).\nYou need to be root.\n",
- strerror(errno));
+ fprintf(stderr, "ERROR: Could not get IO privileges (%s).\nYou need to be root.\n", strerror(errno));
exit(1);
}
@@ -395,7 +397,7 @@
pci_scan_bus(pacc); /* We want to get the list of devices */
/* Open the memory device UNCACHED. That's important for MMIO. */
- if ((fd_mem = open(MEM_DEV, O_RDWR|O_SYNC)) < 0) {
+ if ((fd_mem = open(MEM_DEV, O_RDWR | O_SYNC)) < 0) {
perror("Error: Can not access memory using " MEM_DEV
". You need to be root.");
exit(1);
@@ -420,7 +422,8 @@
board_flash_enable(lb_vendor, lb_part);
for (i = 0; i < ARRAY_SIZE(flashes); i++) {
- flashes[i] = probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0);
+ flashes[i] =
+ probe_flash(i ? flashes[i - 1] + 1 : flashchips, 0);
if (!flashes[i])
for (i++; i < ARRAY_SIZE(flashes); i++)
flashes[i] = NULL;
@@ -468,7 +471,8 @@
if (exclude_end_position - exclude_start_position > 0)
memset(buf + exclude_start_position, 0,
- exclude_end_position - exclude_start_position);
+ exclude_end_position -
+ exclude_start_position);
fwrite(buf, sizeof(char), size, image);
fclose(image);
diff --git a/ichspi.c b/ichspi.c
index 93887b3..095d53a 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -131,14 +131,14 @@
static inline uint32_t REGREAD32(int X)
{
volatile uint32_t regval;
- regval = *(volatile uint32_t *) ((uint8_t *) spibar + X);
+ regval = *(volatile uint32_t *)((uint8_t *) spibar + X);
return regval;
}
static inline uint16_t REGREAD16(int X)
{
volatile uint16_t regval;
- regval = *(volatile uint16_t *) ((uint8_t *) spibar + X);
+ regval = *(volatile uint16_t *)((uint8_t *) spibar + X);
return regval;
}
@@ -184,13 +184,13 @@
preop = (op->preop[0]);
/* 8:16 Prefix Opcode 2 */
preop |= ((uint16_t) op->preop[1]) << 8;
-
+
/* Program Opcode Types 0 - 7 */
optype = 0;
for (a = 0; a < 8; a++) {
optype |= ((uint16_t) op->opcode[a].spi_type) << (a * 2);
}
-
+
/* Program Allowable Opcodes 0 - 3 */
opmenu[0] = 0;
for (a = 0; a < 4; a++) {
@@ -204,8 +204,8 @@
}
switch (flashbus) {
- case BUS_TYPE_ICH7_SPI:
- case BUS_TYPE_VIA_SPI:
+ case BUS_TYPE_ICH7_SPI:
+ case BUS_TYPE_VIA_SPI:
REGWRITE16(ICH7_REG_PREOP, preop);
REGWRITE16(ICH7_REG_OPTYPE, optype);
REGWRITE32(ICH7_REG_OPMENU, opmenu[0]);
@@ -328,7 +328,6 @@
return 0;
}
-
static int ich9_run_opcode(uint8_t nr, OPCODE op, uint32_t offset,
uint8_t datalength, uint8_t * data)
{
@@ -452,8 +451,7 @@
static int ich_spi_erase_block(struct flashchip *flash, int offset)
{
- printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n",
- offset, 1);
+ printf_debug("ich_spi_erase_block: offset=%d, sectors=%d\n", offset, 1);
if (run_opcode(2, curopcodes->opcode[2], offset, 0, NULL) != 0) {
printf_debug("Error erasing sector at 0x%x", offset);
@@ -465,7 +463,8 @@
return 0;
}
-static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset, int maxdata)
+static int ich_spi_read_page(struct flashchip *flash, uint8_t * buf, int offset,
+ int maxdata)
{
int page_size = flash->page_size;
uint32_t remaining = flash->page_size;
@@ -577,8 +576,9 @@
maxdata = 16;
for (j = 0; j < erase_size / page_size; j++) {
- ich_spi_write_page(flash, (void *)(buf + (i * erase_size) + (j * page_size)),
- (i * erase_size) + (j * page_size), maxdata);
+ ich_spi_write_page(flash,
+ (void *)(buf + (i * erase_size) + (j * page_size)),
+ (i * erase_size) + (j * page_size), maxdata);
}
}
diff --git a/it87spi.c b/it87spi.c
index d1dd1d6..dd79b93 100644
--- a/it87spi.c
+++ b/it87spi.c
@@ -33,7 +33,6 @@
#define ITE_SUPERIO_PORT1 0x2e
#define ITE_SUPERIO_PORT2 0x4e
-
uint16_t it8716f_flashport = 0;
/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
int fast_spi = 1;
@@ -85,15 +84,15 @@
/* NOLDN, reg 0x24, mask out lowest bit (suspend) */
tmp = regval(port, 0x24) & 0xFE;
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
- 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
+ 0xFFFE0000, 0xFFFFFFFF, (tmp & 1 << 1) ? "en" : "dis");
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
- 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
+ 0x000E0000, 0x000FFFFF, (tmp & 1 << 1) ? "en" : "dis");
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
- 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
+ 0xFFEE0000, 0xFFEFFFFF, (tmp & 1 << 2) ? "en" : "dis");
printf("Serial flash segment 0x%08x-0x%08x %sabled\n",
- 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
+ 0xFFF80000, 0xFFFEFFFF, (tmp & 1 << 3) ? "en" : "dis");
printf("LPC write to serial flash %sabled\n",
- (tmp & 1 << 4) ? "en" : "dis");
+ (tmp & 1 << 4) ? "en" : "dis");
/* If any serial flash segment is enabled, enable writing. */
if ((tmp & 0xe) && (!(tmp & 1 << 4))) {
printf("Enabling LPC write to serial flash\n");
@@ -123,13 +122,17 @@
return (!it8716f_flashport);
}
-/* The IT8716F only supports commands with length 1,2,4,5 bytes including
- command byte and can not read more than 3 bytes from the device.
- This function expects writearr[0] to be the first byte sent to the device,
- whereas the IT8716F splits commands internally into address and non-address
- commands with the address in inverse wire order. That's why the register
- ordering in case 4 and 5 may seem strange. */
-int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
+/*
+ * The IT8716F only supports commands with length 1,2,4,5 bytes including
+ * command byte and can not read more than 3 bytes from the device.
+ *
+ * This function expects writearr[0] to be the first byte sent to the device,
+ * whereas the IT8716F splits commands internally into address and non-address
+ * commands with the address in inverse wire order. That's why the register
+ * ordering in case 4 and 5 may seem strange.
+ */
+int it8716f_spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr)
{
uint8_t busy, writeenc;
int i;
@@ -139,7 +142,7 @@
} while (busy);
if (readcnt > 3) {
printf("%s called with unsupported readcnt %i.\n",
- __FUNCTION__, readcnt);
+ __FUNCTION__, readcnt);
return 1;
}
switch (writecnt) {
@@ -169,34 +172,36 @@
break;
default:
printf("%s called with unsupported writecnt %i.\n",
- __FUNCTION__, writecnt);
+ __FUNCTION__, writecnt);
return 1;
}
- /* Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
+ /*
+ * Start IO, 33 or 16 MHz, readcnt input bytes, writecnt output bytes.
* Note:
* We can't use writecnt directly, but have to use a strange encoding.
- */
- OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4) | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
+ */
+ OUTB(((0x4 + (fast_spi ? 1 : 0)) << 4)
+ | ((readcnt & 0x3) << 2) | (writeenc), it8716f_flashport);
if (readcnt > 0) {
do {
busy = INB(it8716f_flashport) & 0x80;
} while (busy);
- for (i = 0; i < readcnt; i++) {
+ for (i = 0; i < readcnt; i++)
readarr[i] = INB(it8716f_flashport + 5 + i);
- }
}
return 0;
}
/* Page size is usually 256 bytes */
-static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios) {
+static void it8716f_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
+{
int i;
spi_write_enable();
- OUTB(0x06 , it8716f_flashport + 1);
+ OUTB(0x06, it8716f_flashport + 1);
OUTB(((2 + (fast_spi ? 1 : 0)) << 4), it8716f_flashport);
for (i = 0; i < 256; i++) {
bios[256 * block + i] = buf[256 * block + i];
@@ -217,6 +222,7 @@
{
int total_size = 1024 * flash->total_size;
int i;
+
fast_spi = 0;
spi_disable_blockprotect();
@@ -228,6 +234,7 @@
}
/* resume normal ops... */
OUTB(0x20, it8716f_flashport);
+
return 0;
}
@@ -251,19 +258,23 @@
} else {
memcpy(buf, (const char *)flash->virtual_memory, total_size);
}
+
return 0;
}
-int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf) {
+int it8716f_spi_chip_write(struct flashchip *flash, uint8_t *buf)
+{
int total_size = 1024 * flash->total_size;
int i;
+
if (total_size > 512 * 1024) {
it8716f_over512k_spi_chip_write(flash, buf);
} else {
for (i = 0; i < total_size / 256; i++) {
- it8716f_spi_page_program(i, buf, (uint8_t *)flash->virtual_memory);
+ it8716f_spi_page_program(i, buf,
+ (uint8_t *)flash->virtual_memory);
}
}
+
return 0;
}
-
diff --git a/layout.c b/layout.c
index 668781b..ef09582 100644
--- a/layout.c
+++ b/layout.c
@@ -75,13 +75,13 @@
printf("Flash image seems to be a legacy BIOS. Disabling checks.\n");
return 0;
}
-
+
mb_part = (char *)(bios + size - mb_part_offset);
mb_vendor = (char *)(bios + size - mb_vendor_offset);
if (!isprint((unsigned char)*mb_part) ||
!isprint((unsigned char)*mb_vendor)) {
printf("Flash image seems to have garbage in the ID location."
- " Disabling checks.\n");
+ " Disabling checks.\n");
return 0;
}
@@ -189,7 +189,7 @@
return i;
}
}
- printf("not found.\n"); // Not found. Error.
+ printf("not found.\n"); // Not found. Error.
return -1;
}
diff --git a/pm49fl00x.c b/pm49fl00x.c
index ed2fed0..fe8b974 100644
--- a/pm49fl00x.c
+++ b/pm49fl00x.c
@@ -26,14 +26,13 @@
extern int exclude_start_page, exclude_end_page;
void write_lockbits_49fl00x(volatile uint8_t *bios, int size,
- unsigned char bits, int block_size)
+ unsigned char bits, int block_size)
{
int i, left = size;
for (i = 0; left >= block_size; i++, left -= block_size) {
-
/* pm49fl002 */
- if (block_size == 16384 && i%2)
+ if (block_size == 16384 && i % 2)
continue;
*(bios + (i * block_size) + 2) = bits;
@@ -43,7 +42,7 @@
int probe_49fl00x(struct flashchip *flash)
{
int ret = probe_jedec(flash);
-
+
if (ret == 1)
map_flash_registers(flash);
@@ -58,9 +57,13 @@
volatile uint8_t *bios = flash->virtual_memory;
/* unprotected */
- write_lockbits_49fl00x(flash->virtual_registers, total_size, 0, page_size);
+ write_lockbits_49fl00x(flash->virtual_registers,
+ total_size, 0, page_size);
- //erase_chip_jedec will not work ... datasheet says "Chip erase is available in A/A Mux Mode only"
+ /*
+ * erase_chip_jedec() will not work... Datasheet says
+ * "Chip erase is available in A/A Mux Mode only".
+ */
printf("Erasing page: ");
for (i = 0; i < total_size / page_size; i++) {
if ((i >= exclude_start_page) && (i < exclude_end_page))
@@ -75,7 +78,8 @@
printf("\n");
/* protected */
- write_lockbits_49fl00x(flash->virtual_registers, total_size, 1, page_size);
+ write_lockbits_49fl00x(flash->virtual_registers,
+ total_size, 1, page_size);
return 0;
}
@@ -88,7 +92,8 @@
volatile uint8_t *bios = flash->virtual_memory;
/* unprotected */
- write_lockbits_49fl00x(flash->virtual_registers, total_size, 0, page_size);
+ write_lockbits_49fl00x(flash->virtual_registers, total_size, 0,
+ page_size);
printf("Programming page: ");
for (i = 0; i < total_size / page_size; i++) {
@@ -106,9 +111,10 @@
fflush(stdout);
}
printf("\n");
-
+
/* protected */
- write_lockbits_49fl00x(flash->virtual_registers, total_size, 1, page_size);
+ write_lockbits_49fl00x(flash->virtual_registers, total_size, 1,
+ page_size);
return 0;
}
diff --git a/spi.c b/spi.c
index 6de9da9..0028b4c 100644
--- a/spi.c
+++ b/spi.c
@@ -29,37 +29,41 @@
#include "flash.h"
#include "spi.h"
-
void spi_prettyprint_status_register(struct flashchip *flash);
-int spi_command(unsigned int writecnt, unsigned int readcnt, const unsigned char *writearr, unsigned char *readarr)
+int spi_command(unsigned int writecnt, unsigned int readcnt,
+ const unsigned char *writearr, unsigned char *readarr)
{
switch (flashbus) {
case BUS_TYPE_IT87XX_SPI:
- return it8716f_spi_command(writecnt, readcnt, writearr, readarr);
+ return it8716f_spi_command(writecnt, readcnt, writearr,
+ readarr);
case BUS_TYPE_ICH7_SPI:
case BUS_TYPE_ICH9_SPI:
case BUS_TYPE_VIA_SPI:
- return ich_spi_command(writecnt, readcnt, writearr, readarr);
+ return ich_spi_command(writecnt, readcnt, writearr, readarr);
default:
- printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ printf_debug
+ ("%s called, but no SPI chipset/strapping detected\n",
+ __FUNCTION__);
}
return 1;
}
static int spi_rdid(unsigned char *readarr, int bytes)
{
- const unsigned char cmd[JEDEC_RDID_OUTSIZE] = {JEDEC_RDID};
+ const unsigned char cmd[JEDEC_RDID_OUTSIZE] = { JEDEC_RDID };
if (spi_command(sizeof(cmd), bytes, cmd, readarr))
return 1;
- printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1], readarr[2]);
+ printf_debug("RDID returned %02x %02x %02x.\n", readarr[0], readarr[1],
+ readarr[2]);
return 0;
}
static int spi_res(unsigned char *readarr)
{
- const unsigned char cmd[JEDEC_RES_OUTSIZE] = {JEDEC_RES, 0, 0, 0};
+ const unsigned char cmd[JEDEC_RES_OUTSIZE] = { JEDEC_RES, 0, 0, 0 };
if (spi_command(sizeof(cmd), JEDEC_RES_INSIZE, cmd, readarr))
return 1;
@@ -69,7 +73,7 @@
void spi_write_enable()
{
- const unsigned char cmd[JEDEC_WREN_OUTSIZE] = {JEDEC_WREN};
+ const unsigned char cmd[JEDEC_WREN_OUTSIZE] = { JEDEC_WREN };
/* Send WREN (Write Enable) */
spi_command(sizeof(cmd), 0, cmd, NULL);
@@ -77,7 +81,7 @@
void spi_write_disable()
{
- const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = {JEDEC_WRDI};
+ const unsigned char cmd[JEDEC_WRDI_OUTSIZE] = { JEDEC_WRDI };
/* Send WRDI (Write Disable) */
spi_command(sizeof(cmd), 0, cmd, NULL);
@@ -110,10 +114,10 @@
model_id = (readarr[1] << 8) | readarr[2];
}
- printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id, model_id);
+ printf_debug("%s: id1 0x%x, id2 0x%x\n", __FUNCTION__, manuf_id,
+ model_id);
- if (manuf_id == flash->manufacture_id &&
- model_id == flash->model_id) {
+ if (manuf_id == flash->manufacture_id && model_id == flash->model_id) {
/* Print the status register to tell the
* user about possible write protection.
*/
@@ -130,13 +134,14 @@
return 0;
}
-int probe_spi_rdid(struct flashchip *flash) {
+int probe_spi_rdid(struct flashchip *flash)
+{
return probe_spi_rdid_generic(flash, 3);
}
/* support 4 bytes flash ID */
-int probe_spi_rdid4(struct flashchip *flash) {
-
+int probe_spi_rdid4(struct flashchip *flash)
+{
/* only some SPI chipsets support 4 bytes commands */
switch (flashbus) {
case BUS_TYPE_ICH7_SPI:
@@ -181,7 +186,7 @@
uint8_t spi_read_status_register()
{
- const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = {JEDEC_RDSR};
+ const unsigned char cmd[JEDEC_RDSR_OUTSIZE] = { JEDEC_RDSR };
unsigned char readarr[JEDEC_RDSR_INSIZE];
/* Read Status Register */
@@ -194,17 +199,17 @@
void spi_prettyprint_status_register_common(uint8_t status)
{
printf_debug("Chip status register: Bit 5 / Block Protect 3 (BP3) is "
- "%sset\n", (status & (1 << 5)) ? "" : "not ");
+ "%sset\n", (status & (1 << 5)) ? "" : "not ");
printf_debug("Chip status register: Bit 4 / Block Protect 2 (BP2) is "
- "%sset\n", (status & (1 << 4)) ? "" : "not ");
+ "%sset\n", (status & (1 << 4)) ? "" : "not ");
printf_debug("Chip status register: Bit 3 / Block Protect 1 (BP1) is "
- "%sset\n", (status & (1 << 3)) ? "" : "not ");
+ "%sset\n", (status & (1 << 3)) ? "" : "not ");
printf_debug("Chip status register: Bit 2 / Block Protect 0 (BP0) is "
- "%sset\n", (status & (1 << 2)) ? "" : "not ");
+ "%sset\n", (status & (1 << 2)) ? "" : "not ");
printf_debug("Chip status register: Write Enable Latch (WEL) is "
- "%sset\n", (status & (1 << 1)) ? "" : "not ");
+ "%sset\n", (status & (1 << 1)) ? "" : "not ");
printf_debug("Chip status register: Write In Progress (WIP/BUSY) is "
- "%sset\n", (status & (1 << 0)) ? "" : "not ");
+ "%sset\n", (status & (1 << 0)) ? "" : "not ");
}
/* Prettyprint the status register. Works for
@@ -214,9 +219,9 @@
void spi_prettyprint_status_register_st_m25p(uint8_t status)
{
printf_debug("Chip status register: Status Register Write Disable "
- "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ "(SRWD) is %sset\n", (status & (1 << 7)) ? "" : "not ");
printf_debug("Chip status register: Bit 6 is "
- "%sset\n", (status & (1 << 6)) ? "" : "not ");
+ "%sset\n", (status & (1 << 6)) ? "" : "not ");
spi_prettyprint_status_register_common(status);
}
@@ -235,12 +240,12 @@
"all", "all"
};
printf_debug("Chip status register: Block Protect Write Disable "
- "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
+ "(BPL) is %sset\n", (status & (1 << 7)) ? "" : "not ");
printf_debug("Chip status register: Auto Address Increment Programming "
- "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
+ "(AAI) is %sset\n", (status & (1 << 6)) ? "" : "not ");
spi_prettyprint_status_register_common(status);
printf_debug("Resulting block protection : %s\n",
- bpt[(status & 0x1c) >> 2]);
+ bpt[(status & 0x1c) >> 2]);
}
void spi_prettyprint_status_register(struct flashchip *flash)
@@ -265,11 +270,11 @@
break;
}
}
-
+
int spi_chip_erase_c7(struct flashchip *flash)
{
- const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = {JEDEC_CE_C7};
-
+ const unsigned char cmd[JEDEC_CE_C7_OUTSIZE] = { JEDEC_CE_C7 };
+
spi_disable_blockprotect();
spi_write_enable();
/* Send CE (Chip Erase) */
@@ -289,7 +294,7 @@
*/
int spi_block_erase_d8(const struct flashchip *flash, unsigned long addr)
{
- unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = {JEDEC_BE_D8};
+ unsigned char cmd[JEDEC_BE_D8_OUTSIZE] = { JEDEC_BE_D8 };
cmd[1] = (addr & 0x00ff0000) >> 16;
cmd[2] = (addr & 0x0000ff00) >> 8;
@@ -308,7 +313,7 @@
/* Sector size is usually 4k, though Macronix eliteflash has 64k */
int spi_sector_erase(const struct flashchip *flash, unsigned long addr)
{
- unsigned char cmd[JEDEC_SE_OUTSIZE] = {JEDEC_SE};
+ unsigned char cmd[JEDEC_SE_OUTSIZE] = { JEDEC_SE };
cmd[1] = (addr & 0x00ff0000) >> 16;
cmd[2] = (addr & 0x0000ff00) >> 8;
cmd[3] = (addr & 0x000000ff);
@@ -330,7 +335,8 @@
*/
void spi_write_status_register(int status)
{
- const unsigned char cmd[JEDEC_WRSR_OUTSIZE] = {JEDEC_WRSR, (unsigned char)status};
+ const unsigned char cmd[JEDEC_WRSR_OUTSIZE] =
+ { JEDEC_WRSR, (unsigned char)status };
/* Send WRSR (Write Status Register) */
spi_command(sizeof(cmd), 0, cmd, NULL);
@@ -338,10 +344,11 @@
void spi_byte_program(int address, uint8_t byte)
{
- const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {JEDEC_BYTE_PROGRAM,
- (address>>16)&0xff,
- (address>>8)&0xff,
- (address>>0)&0xff,
+ const unsigned char cmd[JEDEC_BYTE_PROGRAM_OUTSIZE] = {
+ JEDEC_BYTE_PROGRAM,
+ (address >> 16) & 0xff,
+ (address >> 8) & 0xff,
+ (address >> 0) & 0xff,
byte
};
@@ -364,7 +371,8 @@
void spi_nbyte_read(int address, uint8_t *bytes, int len)
{
- const unsigned char cmd[JEDEC_READ_OUTSIZE] = {JEDEC_READ,
+ const unsigned char cmd[JEDEC_READ_OUTSIZE] = {
+ JEDEC_READ,
(address >> 16) & 0xff,
(address >> 8) & 0xff,
(address >> 0) & 0xff,
@@ -376,7 +384,6 @@
int spi_chip_read(struct flashchip *flash, uint8_t *buf)
{
-
switch (flashbus) {
case BUS_TYPE_IT87XX_SPI:
return it8716f_spi_chip_read(flash, buf);
@@ -385,7 +392,9 @@
case BUS_TYPE_VIA_SPI:
return ich_spi_read(flash, buf);
default:
- printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ printf_debug
+ ("%s called, but no SPI chipset/strapping detected\n",
+ __FUNCTION__);
}
return 1;
@@ -401,9 +410,10 @@
case BUS_TYPE_VIA_SPI:
return ich_spi_write(flash, buf);
default:
- printf_debug("%s called, but no SPI chipset/strapping detected\n", __FUNCTION__);
+ printf_debug
+ ("%s called, but no SPI chipset/strapping detected\n",
+ __FUNCTION__);
}
return 1;
}
-
diff --git a/stm50flw0x0x.c b/stm50flw0x0x.c
index bc51c2f..67cf62c 100644
--- a/stm50flw0x0x.c
+++ b/stm50flw0x0x.c
@@ -16,7 +16,6 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
*/
/*
@@ -25,7 +24,6 @@
* ST M50FLW040B (not yet tested)
* ST M50FLW080A
* ST M50FLW080B (not yet tested)
- *
*/
#include <stdio.h>
@@ -93,7 +91,6 @@
return 1;
}
-
static void wait_stm50flw0x0x(volatile uint8_t *bios)
{
uint8_t id1;
@@ -114,50 +111,48 @@
*(volatile uint8_t *)(bios + 0x5555) = 0xAA;
*(volatile uint8_t *)(bios + 0x2AAA) = 0x55;
*(volatile uint8_t *)(bios + 0x5555) = 0xF0;
-
}
/*
* claus.gindhart@kontron.com
* The ST M50FLW080B and STM50FLW080B chips have to be unlocked,
- * before you can erase them or write to them
-*/
+ * before you can erase them or write to them.
+ */
int unlock_block_stm50flw0x0x(struct flashchip *flash, int offset)
{
volatile uint8_t *flash_addr = flash->virtual_registers + 2;
const uint8_t unlock_sector = 0x00;
int j;
- /* These chips have to be unlocked before you can erase
- * them or write to them
- * The size of the locking sectors depends on the type
- * of chip
- *
- * Sometimes, the BIOS does this for you; so you propably
- * dont need to worry about that
- */
+ /*
+ * These chips have to be unlocked before you can erase them or write
+ * to them. The size of the locking sectors depends on the type
+ * of chip.
+ *
+ * Sometimes, the BIOS does this for you; so you propably
+ * don't need to worry about that.
+ */
- /* check, if it's is a top/bottom-block with 4k-sectors */
- /* TODO: What about the other types ? */
+ /* Check, if it's is a top/bottom-block with 4k-sectors. */
+ /* TODO: What about the other types? */
if ((offset == 0) ||
- (offset == (flash->model_id == ST_M50FLW080A ? 0xE0000 : 0x10000))
- || (offset == 0xF0000)) {
+ (offset == (flash->model_id == ST_M50FLW080A ? 0xE0000 : 0x10000))
+ || (offset == 0xF0000)) {
// unlock each 4k-sector
for (j = 0; j < 0x10000; j += 0x1000) {
printf_debug("unlocking at 0x%x\n", offset + j);
*(flash_addr + offset + j) = unlock_sector;
- if (*(flash_addr + offset + j) != unlock_sector)
- {
- printf("Cannot unlock sector @ 0x%x\n",offset + j);
+ if (*(flash_addr + offset + j) != unlock_sector) {
+ printf("Cannot unlock sector @ 0x%x\n",
+ offset + j);
return -1;
}
}
} else {
printf_debug("unlocking at 0x%x\n", offset);
*(flash_addr + offset) = unlock_sector;
- if (*(flash_addr + offset) != unlock_sector)
- {
+ if (*(flash_addr + offset) != unlock_sector) {
printf("Cannot unlock sector @ 0x%x\n", offset);
return -1;
}
@@ -194,9 +189,9 @@
}
int write_page_stm50flw0x0x(volatile uint8_t *bios, uint8_t *src,
- volatile uint8_t *dst, int page_size)
+ volatile uint8_t *dst, int page_size)
{
- int i, rc=0;
+ int i, rc = 0;
volatile uint8_t *d = dst;
uint8_t *s = src;
@@ -236,18 +231,19 @@
*/
int erase_stm50flw0x0x(struct flashchip *flash)
{
- int i,rc=0;
+ int i, rc = 0;
int total_size = flash->total_size * 1024;
int page_size = flash->page_size;
volatile uint8_t *bios = flash->virtual_memory;
printf("Erasing page:\n");
- for (i = 0;(i < total_size / page_size) && (rc==0); i++) {
+ for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
printf
("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
printf("%04d at address: 0x%08x ", i, i * page_size);
rc = unlock_block_stm50flw0x0x(flash, i * page_size);
- if (!rc) rc = erase_block_stm50flw0x0x(flash, i * page_size);
+ if (!rc)
+ rc = erase_block_stm50flw0x0x(flash, i * page_size);
}
printf("\n");
protect_stm50flw0x0x(bios);
@@ -257,13 +253,13 @@
int write_stm50flw0x0x(struct flashchip *flash, uint8_t * buf)
{
- int i,rc=0;
+ int i, rc = 0;
int total_size = flash->total_size * 1024;
int page_size = flash->page_size;
volatile uint8_t *bios = flash->virtual_memory;
printf("Programming page: \n");
- for (i = 0;(i < total_size / page_size) && (rc==0); i++) {
+ for (i = 0; (i < total_size / page_size) && (rc == 0); i++) {
printf
("\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b");
printf("%04d at address: 0x%08x ", i, i * page_size);
@@ -282,9 +278,11 @@
}
rc = unlock_block_stm50flw0x0x(flash, i * page_size);
- if (!rc) rc = erase_block_stm50flw0x0x(flash, i * page_size);
- if (!rc) write_page_stm50flw0x0x(bios, buf + i * page_size,
- bios + i * page_size, page_size);
+ if (!rc)
+ rc = erase_block_stm50flw0x0x(flash, i * page_size);
+ if (!rc)
+ write_page_stm50flw0x0x(bios, buf + i * page_size,
+ bios + i * page_size, page_size);
}
printf("\n");
protect_stm50flw0x0x(bios);
diff --git a/udelay.c b/udelay.c
index e4500ae..5bf441a 100644
--- a/udelay.c
+++ b/udelay.c
@@ -61,6 +61,6 @@
timeusec = 1000000 * (end.tv_sec - start.tv_sec) +
(end.tv_usec - start.tv_usec);
printf_debug("%ldM loops per second, 100 myus = %ld us. ",
- (unsigned long)micro, timeusec);
+ (unsigned long)micro, timeusec);
printf("OK.\n");
}
diff --git a/w29ee011.c b/w29ee011.c
index 3af5be2..d54b038 100644
--- a/w29ee011.c
+++ b/w29ee011.c
@@ -27,7 +27,7 @@
uint8_t id1, id2;
extern char *chip_to_probe;
- if (!chip_to_probe || strcmp(chip_to_probe,"W29EE011")) {
+ if (!chip_to_probe || strcmp(chip_to_probe, "W29EE011")) {
printf_debug("\n===\n");
printf_debug(" Probing disabled for Winbond W29EE011 because the probing sequence puts the\n");
printf_debug(" AMIC A49LF040A in a funky state.\n");
diff --git a/w39v080fa.c b/w39v080fa.c
index 2756859..66534ce 100644
--- a/w39v080fa.c
+++ b/w39v080fa.c
@@ -57,10 +57,11 @@
volatile uint8_t *wrprotect = flash->virtual_registers + offset + 2;
uint8_t locking;
- printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset, *wrprotect);
+ printf_debug("Trying to unlock block @0x%08x = 0x%02x\n", offset,
+ *wrprotect);
locking = *wrprotect;
- switch (locking & 0x7 ) {
+ switch (locking & 0x7) {
case 0:
printf_debug("Full Access.\n");
return 0;
@@ -99,7 +100,7 @@
int i, total_size = flash->total_size * 1024;
volatile uint8_t *bios = flash->virtual_memory;
uint8_t locking;
-
+
/* Are there any hardware restrictions that we can't overcome?
* If flashrom fail here, someone's got to check all those GPIOs.
*/
@@ -121,17 +122,17 @@
printf_debug("Lockout bits:\n");
- if (locking & (1<<2))
+ if (locking & (1 << 2))
fprintf(stderr, "Error: hardware bootblock locking (#TBL).\n");
else
printf_debug("No hardware bootblock locking (good!)\n");
- if (locking & (1<<3))
+ if (locking & (1 << 3))
fprintf(stderr, "Error: hardware block locking (#WP).\n");
else
printf_debug("No hardware block locking (good!)\n");
- if (locking & ((1<<2) | (1<<3)))
+ if (locking & ((1 << 2) | (1 << 3)))
return -1;
/* Unlock the complete chip */
@@ -142,7 +143,8 @@
return 0;
}
-static int erase_sector_winbond_fwhub(volatile uint8_t *bios, unsigned int sector)
+static int erase_sector_winbond_fwhub(volatile uint8_t *bios,
+ unsigned int sector)
{
/* Remember: too much sleep can waste your day. */
@@ -167,7 +169,7 @@
{
int i, total_size = flash->total_size * 1024;
volatile uint8_t *bios = flash->virtual_memory;
-
+
unlock_winbond_fwhub(flash);
printf("Erasing: ");
@@ -197,7 +199,7 @@
return -1;
printf("Programming: ");
- for (i = 0; i < total_size; i+=flash->page_size) {
+ for (i = 0; i < total_size; i += flash->page_size) {
printf("0x%08x\b\b\b\b\b\b\b\b\b\b", i);
write_sector_jedec(bios, buf + i, bios + i, flash->page_size);
}
@@ -205,4 +207,3 @@
return 0;
}
-