spi25_statusreg,flashchips: add SR2 read/write support
This patch adds support for reading and writing the second status
register and enables it on a limited set of flash chips.
Chip support for RDSR2/WRSR2/extended WRSR is represented using feature
flags to be consistent with how other SPI capabilities are represented.
Tested: flashrom -{r,w,E}
Tested: flashrom --wp-{enable,disable,range,list,status} at end of patch series
Tested: logged SR2 read/write values during wp commands
Change-Id: I34a503b0958e8f2f22a2a993a6ea529eb46b41db
Signed-off-by: Nikolai Artemiev <nartemiev@google.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/58570
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/spi.h b/spi.h
index 3f45038..7c393c5 100644
--- a/spi.h
+++ b/spi.h
@@ -126,6 +126,11 @@
#define JEDEC_RDSR_OUTSIZE 0x01
#define JEDEC_RDSR_INSIZE 0x01
+/* Read Status Register 2 */
+#define JEDEC_RDSR2 0x35
+#define JEDEC_RDSR2_OUTSIZE 0x01
+#define JEDEC_RDSR2_INSIZE 0x01
+
/* Status Register Bits */
#define SPI_SR_WIP (0x01 << 0)
#define SPI_SR_WEL (0x01 << 1)
@@ -140,6 +145,12 @@
#define JEDEC_WRSR 0x01
#define JEDEC_WRSR_OUTSIZE 0x02
#define JEDEC_WRSR_INSIZE 0x00
+#define JEDEC_WRSR_EXT_OUTSIZE 0x03
+
+/* Write Status Register 2 */
+#define JEDEC_WRSR2 0x31
+#define JEDEC_WRSR2_OUTSIZE 0x02
+#define JEDEC_WRSR2_INSIZE 0x00
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7