Use the maximum decode size infrastructure
- Detect max FWH size for Intel
631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10.
- Move IDSEL override before decode size checking for the chipsets
listed above or flashrom will complain based on old values.
- Adjust supported flash buses for the chipsets listed above (none of
them supports LPC or Parallel).
- Detect max parallel size for AMD/National Semiconductor CS5530.
- Adjust supported flash buses for CS5530/CS5530A.
- Set board-specific max decode size for Elitegroup K7VTA3.
- Set board-specific max decode size for Shuttle AK38N.
Corresponding to flashrom svn r806.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
diff --git a/board_enable.c b/board_enable.c
index 35972ab..7da1682 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -987,12 +987,20 @@
}
/**
- * Suited for:
- * - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
- * - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
+ * Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
*/
-static int it8705f_write_enable_2e(const char *name)
+static int elitegroup_k7vta3(const char *name)
{
+ max_rom_decode.parallel = 256 * 1024;
+ return it8705f_write_enable(0x2e, name);
+}
+
+/**
+ * Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
+ */
+static int shuttle_ak38n(const char *name)
+{
+ max_rom_decode.parallel = 256 * 1024;
return it8705f_write_enable(0x2e, name);
}
@@ -1233,7 +1241,7 @@
{0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise},
{0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable},
{0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise},
- {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
+ {0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", elitegroup_k7vta3},
{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e},
{0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise},
{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
@@ -1257,7 +1265,7 @@
{0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise},
{0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
{0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e},
- {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},
+ {0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n},
{0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},
{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
diff --git a/chipset_enable.c b/chipset_enable.c
index 333d79d..3994023 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -4,6 +4,7 @@
* Copyright (C) 2000 Silicon Integrated System Corporation
* Copyright (C) 2005-2009 coresystems GmbH
* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
+ * Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -301,34 +302,10 @@
uint32_t fwh_conf;
int i;
char *idsel = NULL;
-
- /* Ignore all legacy ranges below 1 MB. */
- /* FWH_SEL1 */
- fwh_conf = pci_read_long(dev, 0xd0);
- for (i = 7; i >= 0; i--)
- printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
- (0x1ff8 + i) * 0x80000,
- (0x1ff0 + i) * 0x80000,
- (fwh_conf >> (i * 4)) & 0xf);
- /* FWH_SEL2 */
- fwh_conf = pci_read_word(dev, 0xd4);
- for (i = 3; i >= 0; i--)
- printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
- (0xff4 + i) * 0x100000,
- (0xff0 + i) * 0x100000,
- (fwh_conf >> (i * 4)) & 0xf);
- /* FWH_DEC_EN1 */
- fwh_conf = pci_read_word(dev, 0xd8);
- for (i = 7; i >= 0; i--)
- printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
- (0x1ff8 + i) * 0x80000,
- (0x1ff0 + i) * 0x80000,
- (fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
- for (i = 3; i >= 0; i--)
- printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
- (0xff4 + i) * 0x100000,
- (0xff0 + i) * 0x100000,
- (fwh_conf >> i) & 0x1 ? "en" : "dis");
+ int tmp;
+ int max_decode_fwh_idsel = 0;
+ int max_decode_fwh_decode = 0;
+ int contiguous = 1;
if (programmer_param)
idsel = strstr(programmer_param, "fwh_idsel=");
@@ -341,8 +318,76 @@
printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
pci_write_long(dev, 0xd0, fwh_conf);
pci_write_word(dev, 0xd4, fwh_conf);
+ /* FIXME: Decode settings are not changed. */
}
+ /* Ignore all legacy ranges below 1 MB.
+ * We currently only support flashing the chip which responds to
+ * IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
+ * have to be adjusted.
+ */
+ /* FWH_SEL1 */
+ fwh_conf = pci_read_long(dev, 0xd0);
+ for (i = 7; i >= 0; i--) {
+ tmp = (fwh_conf >> (i * 4)) & 0xf;
+ printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
+ (0x1ff8 + i) * 0x80000,
+ (0x1ff0 + i) * 0x80000,
+ tmp);
+ if ((tmp == 0) && contiguous) {
+ max_decode_fwh_idsel = (8 - i) * 0x80000;
+ } else {
+ contiguous = 0;
+ }
+ }
+ /* FWH_SEL2 */
+ fwh_conf = pci_read_word(dev, 0xd4);
+ for (i = 3; i >= 0; i--) {
+ tmp = (fwh_conf >> (i * 4)) & 0xf;
+ printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
+ (0xff4 + i) * 0x100000,
+ (0xff0 + i) * 0x100000,
+ tmp);
+ if ((tmp == 0) && contiguous) {
+ max_decode_fwh_idsel = (8 - i) * 0x100000;
+ } else {
+ contiguous = 0;
+ }
+ }
+ contiguous = 1;
+ /* FWH_DEC_EN1 */
+ fwh_conf = pci_read_word(dev, 0xd8);
+ for (i = 7; i >= 0; i--) {
+ tmp = (fwh_conf >> (i + 0x8)) & 0x1;
+ printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
+ (0x1ff8 + i) * 0x80000,
+ (0x1ff0 + i) * 0x80000,
+ tmp ? "en" : "dis");
+ if ((tmp == 0) && contiguous) {
+ max_decode_fwh_decode = (8 - i) * 0x80000;
+ } else {
+ contiguous = 0;
+ }
+ }
+ for (i = 3; i >= 0; i--) {
+ tmp = (fwh_conf >> i) & 0x1;
+ printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
+ (0xff4 + i) * 0x100000,
+ (0xff0 + i) * 0x100000,
+ tmp ? "en" : "dis");
+ if ((tmp == 0) && contiguous) {
+ max_decode_fwh_decode = (8 - i) * 0x100000;
+ } else {
+ contiguous = 0;
+ }
+ }
+ max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
+ printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
+
+ /* If we're called by enable_flash_ich_dc_spi, it will override
+ * buses_supported anyway.
+ */
+ buses_supported = CHIP_BUSTYPE_FWH;
return enable_flash_ich(dev, name, 0xdc);
}
@@ -355,6 +400,7 @@
{
uint32_t mmio_base;
+ /* Do we really need no write enable? */
mmio_base = (pci_read_long(dev, 0xbc)) << 8;
printf_debug("MMIO base at = 0x%x\n", mmio_base);
spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
@@ -409,8 +455,7 @@
*/
if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
- /* Not sure if it speaks LPC as well. */
- buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
+ buses_supported = CHIP_BUSTYPE_FWH;
/* No further SPI initialization required */
return ret;
}
@@ -422,16 +467,14 @@
spibar_offset = 0x3020;
break;
case 8:
- /* Not sure if it speaks LPC as well. */
- buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
+ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3020;
break;
case 9:
case 10:
default: /* Future version might behave the same */
- /* Not sure if it speaks LPC as well. */
- buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
+ buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
spi_controller = SPI_CONTROLLER_ICH9;
spibar_offset = 0x3800;
break;
@@ -612,14 +655,22 @@
#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
+#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
+#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
#define ROM_WRITE_ENABLE (1 << 1)
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
+#define CS5530_ISA_MASTER (1 << 7)
+#define CS5530_ENABLE_SA2320 (1 << 2)
+#define CS5530_ENABLE_SA20 (1 << 6)
+ buses_supported = CHIP_BUSTYPE_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
+ * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
+ * ignores that region completely.
* Make the configured ROM areas writable.
*/
reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
@@ -633,6 +684,24 @@
reg8 |= BIOS_ROM_POSITIVE_DECODE;
pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
+ reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
+ if (reg8 & CS5530_ISA_MASTER) {
+ /* We have A0-A23 available. */
+ max_rom_decode.parallel = 16 * 1024 * 1024;
+ } else {
+ reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
+ if (reg8 & CS5530_ENABLE_SA2320) {
+ /* We have A0-19, A20-A23 available. */
+ max_rom_decode.parallel = 16 * 1024 * 1024;
+ } else if (reg8 & CS5530_ENABLE_SA20) {
+ /* We have A0-19, A20 available. */
+ max_rom_decode.parallel = 2 * 1024 * 1024;
+ } else {
+ /* A20 and above are not active. */
+ max_rom_decode.parallel = 1024 * 1024;
+ }
+ }
+
return 0;
}