flashchips: Add write protect bits to W25Q64JW...M
https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW
Tested: None
Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62
Signed-off-by: Evan Benn <evanbenn@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71003
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/flashchips.c b/flashchips.c
index 45f6568..6d7a745 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -18176,7 +18176,7 @@
.page_size = 256,
/* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
/* QPI enable 0x38, disable 0xFF */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3,
.tested = TEST_OK_PREW,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
@@ -18204,6 +18204,17 @@
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
+ .tb = {STATUS1, 5, RW},
+ .sec = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
+ .wps = {STATUS3, 2, RW},
+ },
+ .decode_range = decode_range_spi25,
},
{