)]}'
{
  "commit": "1c5d8296f9997e6b773352688fce59c24c1aafd5",
  "tree": "f1ac20fa75e0d2198f7ef0f132d136b89201d751",
  "parents": [
    "b0cae5e30ef780f73b89b8c4ff43c651a3612698"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Oct 25 23:21:02 2024 +0200"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Feb 23 12:05:52 2025 +0000"
  },
  "message": "flashchips: Add Puya P25Q40SH, P25Q80SH, P25Q16SH 3.3V parts\n\nThese are updated versions of the original `H\u0027 chips. They have\na configuration register that is read/written like a third sta-\ntus register, also support QPI,  and have a WPS bit for indivi-\ndual sector protection. Because of the WPS bit, they need their\nown database entries, even though they share the old IDs.\n\nDatasheets used:\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q40SH_Datasheet_V1.9.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q80SH_Datasheet_V1.5.pdf\nhttps://www.puyasemi.com/download_path/%E6%95%B0%E6%8D%AE%E6%89%8B%E5%86%8C/Flash/P25Q16SH_Datasheet_V1.8.pdf\n\nChange-Id: I203bec24b8f4028f50388fb79350d0bf388f404d\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/293\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "239b0eedc2f575b37f01153f653d0d612680f2f1",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "416ca4e3c0c01041e9d979b4a4bbc3a5f5664493",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    }
  ]
}