diff --git a/chipset_enable.c b/chipset_enable.c
index 21990f6..0f854c8 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -210,7 +210,7 @@
 	uint16_t old, new;
 	uint16_t xbcs = 0x4e;	/* X-Bus Chip Select register. */
 
-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	buses_supported = BUS_PARALLEL;
 
 	old = pci_read_word(dev, xbcs);
 
@@ -297,7 +297,7 @@
 	 * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
 	 * FB_DEC_EN2.
 	 */
-	buses_supported = CHIP_BUSTYPE_FWH;
+	buses_supported = BUS_FWH;
 	return enable_flash_ich(dev, name, 0x4e);
 }
 
@@ -414,7 +414,7 @@
 	/* If we're called by enable_flash_ich_dc_spi, it will override
 	 * buses_supported anyway.
 	 */
-	buses_supported = CHIP_BUSTYPE_FWH;
+	buses_supported = BUS_FWH;
 	return enable_flash_ich(dev, name, 0xdc);
 }
 
@@ -434,7 +434,7 @@
        if (new != old)
                rpci_write_byte(dev, 0xd9, new);
 
-	buses_supported = CHIP_BUSTYPE_FWH;
+	buses_supported = BUS_FWH;
        return 0;
 }
 
@@ -487,7 +487,7 @@
 	 * on ICH7 when the southbridge is strapped to LPC
 	 */
 
-	buses_supported = CHIP_BUSTYPE_FWH;
+	buses_supported = BUS_FWH;
 	if (ich_generation == 7) {
 		if(bbs == ICH_STRAP_LPC) {
 			/* No further SPI initialization required */
@@ -498,7 +498,7 @@
 			buses_supported = 0;
 	}
 
-	/* this adds CHIP_BUSTYPE_SPI */
+	/* this adds BUS_SPI */
 	if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
 	        if (!ret)
 		        ret = ERROR_NONFATAL;
@@ -586,7 +586,7 @@
 #define CS5530_ENABLE_SA2320		(1 << 2)
 #define CS5530_ENABLE_SA20		(1 << 6)
 
-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	buses_supported = BUS_PARALLEL;
 	/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
 	 * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
 	 * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@@ -736,7 +736,7 @@
 				(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
 	}
 
-	buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
+	buses_supported = BUS_LPC | BUS_FWH;
 
 	ret = sb600_probe_spi(dev);
 
@@ -822,7 +822,7 @@
 {
 	uint8_t tmp;
 
-	buses_supported = CHIP_BUSTYPE_PARALLEL;
+	buses_supported = BUS_PARALLEL;
 
 	tmp = INB(0xc06);
 	tmp |= 0x1;
@@ -922,7 +922,7 @@
 	switch ((val >> 5) & 0x3) {
 	case 0x0:
 		ret = enable_flash_mcp55(dev, name);
-		buses_supported = CHIP_BUSTYPE_LPC;
+		buses_supported = BUS_LPC;
 		msg_pdbg("Flash bus type is LPC\n");
 		break;
 	case 0x2:
@@ -930,7 +930,7 @@
 		/* SPI is added in mcp6x_spi_init if it works.
 		 * Do we really want to disable LPC in this case?
 		 */
-		buses_supported = CHIP_BUSTYPE_NONE;
+		buses_supported = BUS_NONE;
 		msg_pdbg("Flash bus type is SPI\n");
 		msg_pinfo("SPI on this chipset is WIP. Please report any "
 			  "success or failure by mailing us the verbose "
@@ -938,7 +938,7 @@
 		break;
 	default:
 		/* Should not happen. */
-		buses_supported = CHIP_BUSTYPE_NONE;
+		buses_supported = BUS_NONE;
 		msg_pdbg("Flash bus type is unknown (none)\n");
 		msg_pinfo("Something went wrong with bus type detection.\n");
 		goto out_msg;