tree bf6b57efe06c818f4dbec5d54466930930fa52c0
parent dafd51e22b30b7e13e79567c065e55d30c788fa2
author Nicholas Chin <nic.c3.14@gmail.com> 1666552231 -0600
committer Nico Huber <nico.h@gmx.de> 1677285732 +0000

ch347_spi: Add initial support for the WCH CH347

Add support for the WCH CH347, a high-speed USB to bus converter
supporting multiple protocols interfaces including SPI. Currently only
mode 1 (vendor defined communication interface) is supported, mode 2
(USB HID communication interface) support will be added later. The code
is currently hard coded to use CS1 and a SPI clock of 15 MHz, though
there are 2 CS lines and 6 other GPIO lines available, as well as a
configurable clock divisor for up to 60MHz operation. Support for these
will be exposed through programmer parameters in later commits.

This currently uses the synchronous libusb API. Performance seems to be
alright so far, if it becomes an issue I may switch to the asynchronous
API.

Tested with a MX25L1606E flash chip

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>