)]}'
{
  "commit": "197b7c7b03bc2bbfa6a706812fa69897a3eb7cdb",
  "tree": "bf6b57efe06c818f4dbec5d54466930930fa52c0",
  "parents": [
    "dafd51e22b30b7e13e79567c065e55d30c788fa2"
  ],
  "author": {
    "name": "Nicholas Chin",
    "email": "nic.c3.14@gmail.com",
    "time": "Sun Oct 23 13:10:31 2022 -0600"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sat Feb 25 00:42:12 2023 +0000"
  },
  "message": "ch347_spi: Add initial support for the WCH CH347\n\nAdd support for the WCH CH347, a high-speed USB to bus converter\nsupporting multiple protocols interfaces including SPI. Currently only\nmode 1 (vendor defined communication interface) is supported, mode 2\n(USB HID communication interface) support will be added later. The code\nis currently hard coded to use CS1 and a SPI clock of 15 MHz, though\nthere are 2 CS lines and 6 other GPIO lines available, as well as a\nconfigurable clock divisor for up to 60MHz operation. Support for these\nwill be exposed through programmer parameters in later commits.\n\nThis currently uses the synchronous libusb API. Performance seems to be\nalright so far, if it becomes an issue I may switch to the asynchronous\nAPI.\n\nTested with a MX25L1606E flash chip\n\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nChange-Id: I31b86c41076cc45d4a416a73fa1131350fb745ba\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73106\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
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