)]}'
{
  "commit": "111c380b2502df035057806fb727a724b18c815f",
  "tree": "c552fa6497313652798c34a16f41c2d3e56c6cd3",
  "parents": [
    "b8ee2d63ae9f67bee7d6a2cab11de88128021e51"
  ],
  "author": {
    "name": "Kapil Porwal",
    "email": "kapilporwal@google.com",
    "time": "Fri Dec 09 19:41:27 2022 +0530"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Mon Mar 06 23:36:26 2023 +0000"
  },
  "message": "flashchips.c: Add reg_bits for W25Q256JW_DTR\n\nAdd reg_bits for W25Q256JW_DTR as per the datasheet.\n\nw/o this patch:\nFailed to get WP status: WP operations are not implemented for this chip\n\nw/ this patch:\nflashrom -p internal --wp-range 0x0,0x2000000\nflashrom -p internal --wp-enable\nflashrom -p internal --wp-status\nflashrom -p internal -E \u003c---- failed to erase the flash as WP (which is\nexpected)\n\nSigned-off-by: Kapil Porwal \u003ckapilporwal@google.com\u003e\nChange-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549\nOriginal-Reviewed-by: Subrata Banik \u003csubratabanik@google.com\u003e\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73481\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0872a0ed552b6050111484b95bfdd331970727dd",
      "old_mode": 33188,
      "old_path": "flashchips.c",
      "new_id": "f717e82632579abf2d4576ae18130f7927194120",
      "new_mode": 33188,
      "new_path": "flashchips.c"
    }
  ]
}