flashchips.c: Add reg_bits for W25Q256JW_DTR
Add reg_bits for W25Q256JW_DTR as per the datasheet.
w/o this patch:
Failed to get WP status: WP operations are not implemented for this chip
w/ this patch:
flashrom -p internal --wp-range 0x0,0x2000000
flashrom -p internal --wp-enable
flashrom -p internal --wp-status
flashrom -p internal -E <---- failed to erase the flash as WP (which is
expected)
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I8ac23f706d4293a7d7d11ad6b2f62526fb075367
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/70549
Original-Reviewed-by: Subrata Banik <subratabanik@google.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/73481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
diff --git a/flashchips.c b/flashchips.c
index 0872a0e..f717e82 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -17762,8 +17762,9 @@
.page_size = 256,
/* supports SFDP */
/* OTP: 1024B total, 256B reserved; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
- .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
- .tested = TEST_OK_PREW,
+ .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA | FEATURE_WRSR2
+ | FEATURE_WRSR3,
+ .tested = TEST_OK_PREWB,
.probe = probe_spi_rdid,
.probe_timing = TIMING_ZERO,
.block_erasers =
@@ -17796,6 +17797,16 @@
.write = spi_chip_write_256,
.read = spi_chip_read,
.voltage = {1700, 1950},
+ .reg_bits =
+ {
+ .srp = {STATUS1, 7, RW},
+ .srl = {STATUS2, 0, RW},
+ .bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+ .tb = {STATUS1, 6, RW},
+ .cmp = {STATUS2, 6, RW},
+ .wps = {STATUS3, 2, RW},
+ },
+ .decode_range = decode_range_spi25,
},
{