ichspi: Add Intel Snow Ridge SoC
Hardware looks the same as C740 series / Emmitsburg. The descriptor,
however, has very different frequency settings and different regions
and masters.
The output of `ich_descriptors_tool' tested with an image from Intel
looks reasonable.
Change-Id: I9f9dc4414af63cbe48d22ef2955df28e297d7e4c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.sourcearcade.org/c/flashprog/+/188
diff --git a/chipset_enable.c b/chipset_enable.c
index 2988a60..5a89589 100644
--- a/chipset_enable.c
+++ b/chipset_enable.c
@@ -705,6 +705,7 @@
case CHIPSET_APOLLO_LAKE:
case CHIPSET_GEMINI_LAKE:
case CHIPSET_ELKHART_LAKE:
+ case CHIPSET_SNOW_RIDGE: /* hard coded to 0 (SPI) */
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -1018,6 +1019,12 @@
return enable_flash_pch_spidev(spi_dev, name, CHIPSET_C740_SERIES_EMMITSBURG);
}
+static int enable_flash_snowridge(struct flashprog_programmer *const prog,
+ struct pci_dev *const spi_dev, const char *const name)
+{
+ return enable_flash_pch_spidev(spi_dev, name, CHIPSET_SNOW_RIDGE);
+}
+
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
* These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
*
@@ -2218,6 +2225,7 @@
{0x8086, 0x54a4, ANY_REV, B_S, DEP, "Intel", "Alder Lake-N", enable_flash_pch500},
{0x8086, 0x7a24, ANY_REV, B_S, NT, "Intel", "Raptor Lake-S", enable_flash_pch500},
{0x8086, 0x7aa4, ANY_REV, B_S, NT, "Intel", "Alder Lake-S", enable_flash_pch500},
+ {0x8086, 0x18e0, ANY_REV, B_S, NT, "Intel", "Snow Ridge", enable_flash_snowridge},
#endif
{0},
};