)]}'
{
  "commit": "0b5a70736f59dce25d0f6d71a6dc89a54b680fcd",
  "tree": "990c09b00907579493b355284b5a4d43724824ce",
  "parents": [
    "29c8b5db5da5c0506aaac26fdfd3c8312638a51b"
  ],
  "author": {
    "name": "Sergii Dmytruk",
    "email": "sergii.dmytruk@3mdeb.com",
    "time": "Sun Aug 14 16:51:46 2022 +0300"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Fri Dec 30 01:16:55 2022 +0100"
  },
  "message": "writeprotect.c: skip unnecessary writes\n\n* Don\u0027t write register because of RO and OTP bits.\n* Skip the write of RW bits if register state wouldn\u0027t change by it.\n\nChange-Id: I81d2d3fc0a103ee00ced78838d77fe33a9d3056a\nSigned-off-by: Sergii Dmytruk \u003csergii.dmytruk@3mdeb.com\u003e\nOriginal-Reviewed-on: https://review.coreboot.org/c/flashrom/+/66754\nOriginal-Reviewed-by: Edward O\u0027Callaghan \u003cquasisec@chromium.org\u003e\nOriginal-Reviewed-by: Nikolai Artemiev \u003cnartemiev@google.com\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/71004\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "11219e2617368390260254c4d9d6a17b545ad813",
      "old_mode": 33188,
      "old_path": "writeprotect.c",
      "new_id": "48c5ae6d0e66ccff0991ec52bb14722d89c4cec9",
      "new_mode": 33188,
      "new_path": "writeprotect.c"
    }
  ]
}