spi25_statusreg.c: add SR3 read/write support
Adds support for reading and writing the third status register.
Feature flag is not needed because it would never on its own control
whether SR3 access occurs. If added, it would be in one of three
possible states: wrong, useless or redundant.
Change-Id: Id987c544c02da2b956e6ad2c525265cac8f15be1
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Original-Reviewed-on: https://review.coreboot.org/c/flashrom/+/60230
Original-Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Original-Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Original-Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom-stable/+/70980
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/spi25_statusreg.c b/spi25_statusreg.c
index 6b16839..0f43056 100644
--- a/spi25_statusreg.c
+++ b/spi25_statusreg.c
@@ -66,6 +66,11 @@
}
msg_cerr("Cannot write SR2: unsupported by chip\n");
return 1;
+ case STATUS3:
+ write_cmd[0] = JEDEC_WRSR3;
+ write_cmd[1] = value;
+ write_cmd_len = JEDEC_WRSR3_OUTSIZE;
+ break;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@@ -153,6 +158,9 @@
}
msg_cerr("Cannot read SR2: unsupported by chip\n");
return 1;
+ case STATUS3:
+ read_cmd = JEDEC_RDSR3;
+ break;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;