diff --git a/libflashrom.h b/libflashrom.h
index 2570362..0c007e6 100644
--- a/libflashrom.h
+++ b/libflashrom.h
@@ -129,7 +129,8 @@
 	FLASHROM_WP_ERR_VERIFY_FAILED = 5,
 	FLASHROM_WP_ERR_RANGE_UNSUPPORTED = 6,
 	FLASHROM_WP_ERR_MODE_UNSUPPORTED = 7,
-	FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE = 8
+	FLASHROM_WP_ERR_RANGE_LIST_UNAVAILABLE = 8,
+	FLASHROM_WP_ERR_UNSUPPORTED_STATE = 9,
 };
 
 enum flashrom_wp_mode {
diff --git a/writeprotect.c b/writeprotect.c
index 48c5ae6..e3a1410 100644
--- a/writeprotect.c
+++ b/writeprotect.c
@@ -53,6 +53,25 @@
 	size_t i;
 	enum flashrom_wp_result ret;
 
+	/*
+	 * Write protection select bit (WPS) controls kind of write protection
+	 * that is used by the chip. When set, BP bits are ignored and each
+	 * block/sector has its own WP bit managed by special commands. When
+	 * the bit is set and we can't change it, just bail out until
+	 * implementation is extended to handle this kind of WP.
+	 */
+	if (bit_map->wps.reg != INVALID_REG && bit_map->wps.writability != RW) {
+		bool wps_bit_present;
+		uint8_t wps;
+
+		ret = read_bit(&wps, &wps_bit_present, flash, bit_map->wps);
+		if (ret != FLASHROM_WP_OK)
+			return ret;
+
+		if (wps_bit_present && wps)
+			return FLASHROM_WP_ERR_UNSUPPORTED_STATE;
+	}
+
 	ret = read_bit(&bits->tb,  &bits->tb_bit_present,  flash, bit_map->tb);
 	if (ret != FLASHROM_WP_OK)
 		return ret;
@@ -73,8 +92,6 @@
 	if (ret != FLASHROM_WP_OK)
 		return ret;
 
-	/* Note: WPS bit isn't read here, because it's not part of any range. */
-
 	for (i = 0; i < ARRAY_SIZE(bits->bp); i++) {
 		if (bit_map->bp[i].reg == INVALID_REG)
 			break;