)]}'
{
  "commit": "019810f3fd083df5f6f61d19dda2d252709d02fe",
  "tree": "d9f2f1e6f8e10b6bb1d4b7f56f431f9073942fbc",
  "parents": [
    "6d98aece44f6f3458c79160adf4dddc7f8500378"
  ],
  "author": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Sun Jan 29 17:11:24 2023 +0000"
  },
  "committer": {
    "name": "Nico Huber",
    "email": "nico.h@gmx.de",
    "time": "Tue Feb 21 22:52:42 2023 +0000"
  },
  "message": "chipset_enable: Optionally check PCI revision field\n\nWe used to match compatible chipset devices by vendor and device ID\nonly. On some chipsets, e.g. AMD southbridges / SoCs, this is not\nenough, though, as the device IDs are rarely updated.\n\nIn the case of AMD chipsets, we can identify the chipset with the\nrevision ID of the SMBus device. So we add that field to the chipset\nenable list.\n\nChange-Id: I4021cf8e83c605fde4360c274b39481b1e0ff070\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.coreboot.org/c/flashrom-stable/+/72573\nReviewed-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\nTested-by: build bot (Jenkins) \u003cno-reply@coreboot.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "147ce44f9f20bda94106449a923813485aa3a563",
      "old_mode": 33188,
      "old_path": "chipset_enable.c",
      "new_id": "0d796db142c7d5f5a0ea70f5cc448fcd6fb33215",
      "new_mode": 33188,
      "new_path": "chipset_enable.c"
    },
    {
      "type": "modify",
      "old_id": "2a4a8f4d80889b361ba328286b542e5cc4440cce",
      "old_mode": 33188,
      "old_path": "include/programmer.h",
      "new_id": "bbdbffba4b8023ebc50e06658da3eabffa51e528",
      "new_mode": 33188,
      "new_path": "include/programmer.h"
    }
  ]
}