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refs/changes/99/499/1 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/1 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/1 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/1","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/1 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"732feb414dcb58e9282d25fc8c569d372d179f47","subject":"gma i2c: Update for Tiger Lake","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/732feb414dcb58e9282d25fc8c569d372d179f47"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-04-15 08:57:43.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/6b129b2add95a96e26e6146d5a6d17f23b2ca420"}]},"branch":"refs/heads/main"},"613423e1a761aaf3963d11c9c9fe4e322601a6fe":{"kind":"REWORK","_number":2,"created":"2026-06-09 13:08:33.000000000","uploader":{"_account_id":1000003,"name":"Arthur Heymans","email":"arthur@aheymans.xyz","username":"arthurheymans","avatars":[{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/99/499/2","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/libgfxinit","ref":"refs/changes/99/499/2","commands":{"Branch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2 \u0026\u0026 git checkout -b change-499 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de756532f75d7ee7fd16fc8218292c45db26900","subject":"gma display_probing: Let Port_List_Range grow with Active_Port_Type","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/4de756532f75d7ee7fd16fc8218292c45db26900"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-06-09 13:08:22.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/613423e1a761aaf3963d11c9c9fe4e322601a6fe"}]},"branch":"refs/heads/main"},"da4dcc36387482d91a10e73b66fb992a265da3cb":{"kind":"REWORK","_number":3,"created":"2026-06-09 13:13:19.000000000","uploader":{"_account_id":1000003,"name":"Arthur Heymans","email":"arthur@aheymans.xyz","username":"arthurheymans","avatars":[{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/99/499/3","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/libgfxinit","ref":"refs/changes/99/499/3","commands":{"Branch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3 \u0026\u0026 git checkout -b change-499 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de756532f75d7ee7fd16fc8218292c45db26900","subject":"gma display_probing: Let Port_List_Range grow with Active_Port_Type","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/4de756532f75d7ee7fd16fc8218292c45db26900"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-06-09 13:13:03.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/da4dcc36387482d91a10e73b66fb992a265da3cb"}]},"branch":"refs/heads/main"},"e5f42bf4fa5976f0ba8d94c8e7c049b517d551f3":{"kind":"REWORK","_number":4,"created":"2026-06-09 13:45:44.000000000","uploader":{"_account_id":1000003,"name":"Arthur Heymans","email":"arthur@aheymans.xyz","username":"arthurheymans","avatars":[{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/99/499/4","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/libgfxinit","ref":"refs/changes/99/499/4","commands":{"Branch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4 \u0026\u0026 git checkout -b change-499 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de756532f75d7ee7fd16fc8218292c45db26900","subject":"gma display_probing: Let Port_List_Range grow with Active_Port_Type","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/4de756532f75d7ee7fd16fc8218292c45db26900"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-06-09 13:45:38.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/e5f42bf4fa5976f0ba8d94c8e7c049b517d551f3"}]},"branch":"refs/heads/main"},"570ae692e98c6dcea118ec596c9d9fced6ab411e":{"kind":"REWORK","_number":5,"created":"2026-06-09 14:39:31.000000000","uploader":{"_account_id":1000003,"name":"Arthur Heymans","email":"arthur@aheymans.xyz","username":"arthurheymans","avatars":[{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/99/499/5","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/libgfxinit","ref":"refs/changes/99/499/5","commands":{"Branch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5 \u0026\u0026 git checkout -b change-499 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de756532f75d7ee7fd16fc8218292c45db26900","subject":"gma display_probing: Let Port_List_Range grow with Active_Port_Type","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/4de756532f75d7ee7fd16fc8218292c45db26900"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-06-09 14:39:23.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. Add I9XX_LVDS_Limits; refactor Calculate_Clock_Parameters\n   to take Limits as a parameter, with a new Select_Limits function.\n - VCO: Uses Crestline (CL) VCO tables with different frequencies\n   and divisors than GM45\u0027s Cantiga (CTG) tables.\n - CDClk: GCFGC register decoding uses bits 12:8 minus 1 (3 possible\n   divisor selections), unlike GM45\u0027s single bit 12.\n - No native DisplayPort (SDVO B/C only).\n - No HD Audio (G4X_AUD_VID_DID reads as 0).\n - Has integrated LVDS transmitter (mobile platform).\n - PCI IDs: 0x2a02 (I965_GM), 0x2a12 (I965_GME).\n\nAll implementation details cross-referenced against the Linux kernel\ni915 driver (intel_dpll.c, intel_cdclk.c, intel_display_device.c).\n\nChange-Id: I0d5d698cc1c2aa84778f0fc6c2752cb5ce4f1cb2\nSigned-off-by: Arthur Heymans \u003carthur@aheymans.xyz\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/570ae692e98c6dcea118ec596c9d9fced6ab411e"}]},"branch":"refs/heads/main"},"ddac5912cbc8a44bcbe8de086016255ab36af93e":{"kind":"REWORK","_number":6,"created":"2026-06-17 20:42:40.000000000","uploader":{"_account_id":1000003,"name":"Arthur Heymans","email":"arthur@aheymans.xyz","username":"arthurheymans","avatars":[{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/518bb7353a0a42df698e1736723abc9f.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/99/499/6","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/libgfxinit","ref":"refs/changes/99/499/6","commands":{"Branch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6 \u0026\u0026 git checkout -b change-499 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6","Reset To":"git fetch https://review.sourcearcade.org/libgfxinit refs/changes/99/499/6 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"4de756532f75d7ee7fd16fc8218292c45db26900","subject":"gma display_probing: Let Port_List_Range grow with Active_Port_Type","web_links":[{"name":"browse","url":"/plugins/gitiles/libgfxinit/+/4de756532f75d7ee7fd16fc8218292c45db26900"}]}],"author":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-03-03 17:52:12.000000000","tz":60},"committer":{"name":"Arthur Heymans","email":"arthur@aheymans.xyz","date":"2026-06-16 17:15:07.000000000","tz":120},"subject":"gma g45: Add support for Intel GM965 (Crestline)","message":"gma g45: Add support for Intel GM965 (Crestline)\n\nAdd GM965 as a new CPU type under the G45 generation. GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. 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GM965 shares\nthe GMCH display architecture with G45/GM45 (no PCH, same connector\nregisters) but differs in PLL limits, VCO/CDClk tables, and register\nfield encoding.\n\nKey differences from G45/GM45:\n - PLL limits: Uses i9xx limits (VCO 1.4-2.8 GHz) instead of g4x\n   limits. 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