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14:46:59.000000000","tz":120},"subject":"spi: Implement top-aligned to avoid BBAR hassle","message":"spi: Implement top-aligned to avoid BBAR hassle\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/12f720dcc7299a1bd0a8004eb63cba849d1db821"}]},"branch":"refs/heads/main"},"618c4373c6cd218df440f7da8e487e38c311b8d8":{"kind":"REWORK","_number":2,"created":"2025-02-19 22:49:06.000000000","uploader":{"_account_id":1000000,"name":"Nico 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11:24:33.000000000","tz":60},"subject":"spi: Implement top-aligned to avoid BBAR hassle","message":"spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there  was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected.  This was originally the only read-\nprotection mechanism, introduced with ICH7.  The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits.  Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible.  The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits.  Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone,  we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n    Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/618c4373c6cd218df440f7da8e487e38c311b8d8"}]},"branch":"refs/heads/main"},"61167ecf2abd2e2c0f4e8097f4eda5b6c332c518":{"kind":"REWORK","_number":3,"created":"2025-03-08 14:27:45.000000000","uploader":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/96/74896/3","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/96/74896/3","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/3 \u0026\u0026 git checkout -b change-74896 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/96/74896/3","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"6c77a76d3bfffb6d2ef55df619672720bb4185e1","subject":"at45db: Use .prepare_access hook for non-power-of-2 preparations","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/6c77a76d3bfffb6d2ef55df619672720bb4185e1"}]}],"author":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2023-02-15 01:55:23.000000000","tz":60},"committer":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2025-03-08 14:10:11.000000000","tz":60},"subject":"spi: Implement top-aligned to avoid BBAR hassle","message":"spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there  was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected.  This was originally the only read-\nprotection mechanism, introduced with ICH7.  The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits.  Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible.  The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits.  Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone,  we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n    Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/61167ecf2abd2e2c0f4e8097f4eda5b6c332c518"}]},"branch":"refs/heads/main"},"b9d6170b80e780fb239f07a5a126e7983cd13c66":{"kind":"TRIVIAL_REBASE","_number":4,"created":"2026-02-12 21:01:29.000000000","uploader":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/96/74896/4","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/96/74896/4","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/4 \u0026\u0026 git checkout -b change-74896 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/96/74896/4","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"ad89f20bafe449b2f46bd63ae23aafb6af8daa7b","subject":"at45db: Use .prepare_access hook for non-power-of-2 preparations","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/ad89f20bafe449b2f46bd63ae23aafb6af8daa7b"}]}],"author":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2023-02-15 01:55:23.000000000","tz":60},"committer":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2026-02-08 20:45:40.000000000","tz":60},"subject":"spi: Implement top-aligned to avoid BBAR hassle","message":"spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there  was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected.  This was originally the only read-\nprotection mechanism, introduced with ICH7.  The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits.  Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible.  The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits.  Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone,  we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n    Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/b9d6170b80e780fb239f07a5a126e7983cd13c66"}]},"branch":"refs/heads/main"},"e3f648c3146be28c642782b11187011dfd6f258d":{"kind":"TRIVIAL_REBASE_WITH_MESSAGE_UPDATE","_number":5,"created":"2026-02-14 22:42:55.000000000","uploader":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/96/74896/5","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/96/74896/5","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/5 \u0026\u0026 git checkout -b change-74896 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/96/74896/5","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/96/74896/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"32f1ea8df501b41362058bb699a7ea96482e4db3","subject":"at45db: Use .prepare_access hook for non-power-of-2 preparations","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/32f1ea8df501b41362058bb699a7ea96482e4db3"}]}],"author":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2023-02-15 01:55:23.000000000","tz":60},"committer":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2026-02-14 22:42:55.000000000","tz":0},"subject":"spi: Implement top-aligned to avoid BBAR hassle","message":"spi: Implement top-aligned to avoid BBAR hassle\n\nThe BBAR quirk in `ichspi\u0027 is the only case left where we need a flash\ncontext in the SPI `.send_command\u0027 functions. Our Git history suggests\nthat the elaborate calculation there  was not added for an encountered\nsetup but rather all possible settings of BBAR [1]. There are only few\nsettings that make sense, however.\n\nBBAR sets a simple address boundary. Reads for any flash address below\nthe BBAR setting will be rejected.  This was originally the only read-\nprotection mechanism, introduced with ICH7.  The ICH7 datasheet states\nthat upper bits, above the flash chip\u0027s size, should be set to all 1s.\nThis makes sense, as otherwise the read-protection could be circumven-\nted by setting a higher address above BBAR, where the flash chip would\nsimply ignore the most significant bits.  Conversely, this requires us\nto \"lift\" the flash addresses when the BBAR is configured properly. We\ncan achieve this by top-aligning all addresses.\n\nNewer chipsets have protected-range registers (PRx) now, that allow to\nconfigure read protection. Also the descriptor mode was introduced. So\nflash addresses have to match the descriptor regions, and lifting them\nisn\u0027t feasible.  The BBAR register was still around until Wilcat Point\n(PCH9), though, probably useless, and without the note about upper ad-\ndress bits.  Odd though, since [2], we only consider the BBAR on newer\nchipsets when in descriptor mode.\n\nAs the BBAR protection seems unlikely on newer chipsets, and the quirk\nhandling error-prone,  we\u0027ll only change addresses on ICH7 and similar\nold chipsets. We don\u0027t want the dependency on the flash context, hence\nlet the generic `spi25\u0027 code top align the addresses.\n\n[1] commit ed098d62d66d (spi: Move ICH BBAR quirk out of the way)\n[2] commit 4095ed797f87 (Add support for Intel Silvermont: Bay Trail,\n    Rangeley and Avoton)\n\nChange-Id: Ic6f6f5a24d89d4a1ebe2b99f08aabfcd65df129f\nSigned-off-by: Nico Huber \u003cnico.h@gmx.de\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/74896\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/e3f648c3146be28c642782b11187011dfd6f258d"}]},"branch":"refs/heads/main","description":"Rebase","conflicts":{"ours":"b9d6170b80e780fb239f07a5a126e7983cd13c66","theirs":"32f1ea8df501b41362058bb699a7ea96482e4db3","contains_conflicts":false}}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"CLOSED","labels":[{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]}},{"label":"Verified","status":"OK","applied_by":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[],"atom_explanations":{}}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"],"failing_atoms":[],"atom_explanations":{}}}]}