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were changed between the latest approved patch-set and the submitted one.\n","accounts_in_message":[],"_revision_number":5}],"current_revision_number":5,"current_revision":"dac4239136fcbfdd29e5f71cfe8d570d5be26494","revisions":{"2018c54f2c23108599cba0c5fb818f7f8f1ccbdc":{"kind":"REWORK","_number":1,"created":"2024-08-18 03:39:39.000000000","uploader":{"_account_id":1000010,"name":"Nicholas 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By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/2018c54f2c23108599cba0c5fb818f7f8f1ccbdc"}]},"branch":"refs/heads/main"},"c709bb3461055b38f4489216d55d1c61167e2778":{"kind":"REWORK","_number":2,"created":"2024-08-18 03:41:41.000000000","uploader":{"_account_id":1000010,"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","username":"nic3-14159","avatars":[{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/44/244/2","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/44/244/2","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/2 \u0026\u0026 git checkout -b change-244 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/2 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/2 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/2 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/44/244/2","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/2 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"56d236bda45dfe9069fd29773965aa269506e0a9","subject":"chipset_enable: Add some newer AMD code names","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/56d236bda45dfe9069fd29773965aa269506e0a9"}]}],"author":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-07-31 02:01:59.000000000","tz":-360},"committer":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-08-18 03:41:15.000000000","tz":-360},"subject":"ch347_spi: Add \u0027spimode\u0027 parameter","message":"ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. 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I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/c709bb3461055b38f4489216d55d1c61167e2778"}]},"branch":"refs/heads/main"},"ff7015a5bd7c557054a92ff0e273bab1a99e6d54":{"kind":"REWORK","_number":3,"created":"2024-08-18 13:58:03.000000000","uploader":{"_account_id":1000010,"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","username":"nic3-14159","avatars":[{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/44/244/3","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/44/244/3","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/3 \u0026\u0026 git checkout -b change-244 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/3 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/3 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/3 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/44/244/3","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/3 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"56d236bda45dfe9069fd29773965aa269506e0a9","subject":"chipset_enable: Add some newer AMD code names","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/56d236bda45dfe9069fd29773965aa269506e0a9"}]}],"author":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-07-31 02:01:59.000000000","tz":-360},"committer":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-08-18 13:57:42.000000000","tz":-360},"subject":"ch347_spi: Add \u0027spimode\u0027 parameter","message":"ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration. The CH347 probably has\nsome setup/hold time issues at high speeds such that running it in a\ndifferent mode allows it to sample data properly.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/ff7015a5bd7c557054a92ff0e273bab1a99e6d54"}]},"branch":"refs/heads/main"},"9b5c6ae513a3fe954fef3e2c656e654cde7bce39":{"kind":"NO_CODE_CHANGE","_number":4,"created":"2024-08-18 15:25:41.000000000","uploader":{"_account_id":1000010,"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","username":"nic3-14159","avatars":[{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/f13f0d20eaa2ed381f24a2d16d3129e1.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/44/244/4","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/44/244/4","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/4 \u0026\u0026 git checkout -b change-244 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/4 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/4 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/4 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/44/244/4","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/4 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"56d236bda45dfe9069fd29773965aa269506e0a9","subject":"chipset_enable: Add some newer AMD code names","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/56d236bda45dfe9069fd29773965aa269506e0a9"}]}],"author":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-07-31 02:01:59.000000000","tz":-360},"committer":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-08-18 15:25:41.000000000","tz":0},"subject":"ch347_spi: Add \u0027spimode\u0027 parameter","message":"ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/9b5c6ae513a3fe954fef3e2c656e654cde7bce39"}]},"branch":"refs/heads/main","description":"Edit commit message"},"dac4239136fcbfdd29e5f71cfe8d570d5be26494":{"kind":"NO_CODE_CHANGE","_number":5,"created":"2024-08-19 10:58:13.000000000","uploader":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]},"ref":"refs/changes/44/244/5","fetch":{"anonymous http":{"url":"https://review.sourcearcade.org/flashprog","ref":"refs/changes/44/244/5","commands":{"Branch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/5 \u0026\u0026 git checkout -b change-244 FETCH_HEAD","Checkout":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/5 \u0026\u0026 git checkout FETCH_HEAD","Cherry Pick":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/5 \u0026\u0026 git cherry-pick FETCH_HEAD","Format Patch":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/5 \u0026\u0026 git format-patch -1 --stdout FETCH_HEAD","Pull":"git pull https://review.sourcearcade.org/flashprog refs/changes/44/244/5","Reset To":"git fetch https://review.sourcearcade.org/flashprog refs/changes/44/244/5 \u0026\u0026 git reset --hard FETCH_HEAD"}}},"commit":{"parents":[{"commit":"56d236bda45dfe9069fd29773965aa269506e0a9","subject":"chipset_enable: Add some newer AMD code names","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/56d236bda45dfe9069fd29773965aa269506e0a9"}]}],"author":{"name":"Nicholas Chin","email":"nic.c3.14@gmail.com","date":"2024-07-31 02:01:59.000000000","tz":-360},"committer":{"name":"Nico Huber","email":"nico.h@gmx.de","date":"2024-08-19 10:58:13.000000000","tz":0},"subject":"ch347_spi: Add \u0027spimode\u0027 parameter","message":"ch347_spi: Add \u0027spimode\u0027 parameter\n\nThis allows the SPI mode (clock polarity and phase) of the CH347 to be\nselected. By default mode 0 is used, as most flash chips are compatible\nwith this mode. I have noticed that the CH347 is able to work at higher\nclock speeds with some chips when set to mode 1, despite the chip not\nofficially having support for this configuration.\n\nChange-Id: I7938519e23e9e014c016f9d7f130d1ac191a09fa\nSigned-off-by: Nicholas Chin \u003cnic.c3.14@gmail.com\u003e\nReviewed-on: https://review.sourcearcade.org/c/flashprog/+/244\nReviewed-by: Nico Huber \u003cnico.h@gmx.de\u003e\nTested-by: Nico Huber \u003cnico.h@gmx.de\u003e\n","web_links":[{"name":"browse","url":"/plugins/gitiles/flashprog/+/dac4239136fcbfdd29e5f71cfe8d570d5be26494"}]},"branch":"refs/heads/main","description":"Rebase"}},"requirements":[],"submit_records":[{"rule_name":"gerrit~DefaultSubmitRule","status":"CLOSED","labels":[{"label":"Code-Review","status":"OK","applied_by":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]}},{"label":"Verified","status":"OK","applied_by":{"_account_id":1000000,"name":"Nico Huber","email":"nico.h@gmx.de","username":"icon","avatars":[{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d32","height":32},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d56","height":56},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d100","height":100},{"url":"https://www.gravatar.com/avatar/60d420b5d650d48b86d6921a9f683b64.jpg?d\u003didenticon\u0026r\u003dpg\u0026s\u003d120","height":120}]}}]}],"submit_requirements":[{"name":"Verified","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Verified\u003dMAX -label:Verified\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Verified\u003dMAX","-label:Verified\u003dMIN"],"failing_atoms":[],"atom_explanations":{}}},{"name":"Code-Review","status":"SATISFIED","is_legacy":true,"submittability_expression_result":{"expression":"label:Code-Review\u003dMAX -label:Code-Review\u003dMIN","fulfilled":true,"status":"PASS","passing_atoms":["label:Code-Review\u003dMAX","-label:Code-Review\u003dMIN"],"failing_atoms":[],"atom_explanations":{}}}]}